HFBR-5963ALZ Avago Technologies US Inc., HFBR-5963ALZ Datasheet - Page 12

• Manufacturer Part Number: HFBR-5963ALZ
• Description: TXRX MMF FE ATM SONET OC-3 2X5
• Manufacturer: Avago Technologies US Inc.
• Series: -r

Specifications of HFBR-5963ALZ

• Applications: Ethernet
• Data Rate: 155MBd
• Wavelength: 1300nm
• Voltage - Supply: 2.97 V ~ 3.63 V
• Connector Type: LC Duplex
• Mounting Type: Through Hole
• Supply Voltage: 3.3V
• Wavelength Typ: 1300nm
• Leaded Process Compatible: Yes
• Product: Transceiver
• Maximum Rise Time: 3 ns, 2.2 ns
• Maximum Fall Time: 3 ns, 2.2 ns
• Pulse Width Distortion: 0.4 ns, 0.3 ns
• Maximum Output Current: 50 mA
• Operating Supply Voltage: 2.97 V to 3.63 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: DIP-10 with Connector
• Function: Transceivers for ATM, FDDI, Fast Ethernet and SONET OC-3/SDH STM-1 with LC connector.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: Multimode Glass
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

12. The optical rise and fall times are measured from 10% to 90% when
13a. Systematic Jitter contributed by the transmitter is defined as the
13b. Duty Cycle Distortion contributed by the transmitter is measured at
13c. Data Dependent Jitter contributed by the transmitter is specified
14a. Random Jitter contributed by the transmitter is specified with a
14b. Random Jitter contributed by the transmitter is specified with an
15a. This specification is intended to indicate the performance of the
15b. This specification is intended to indicate the performance of the
• At the Beginning of Life (BOL)
• Over the specified operating temperature and voltage ranges
• Input symbol pattern is the FDDI test pattern defined in FDDI PMD
• Receiver data window time-width is 2.13 ns or greater and centered
12
the transmitter is driven by a 25 MBd (12.5 MHz square-wave) input
signal. The ANSI T1E1.2 committee has designated the possibility of
defining an eye pattern mask for the transmitter optical output as
an item for further study. Avago will incorporate this requirement
into the specifications for these products if it is defined. The HFBR-
59XXL products typically comply with the template requirements of
CCITT (now ITU-T) G.957 Section 3.2.5, Figure 5 for the STM- 1 rate,
excluding the optical receiver filter normally associated with single
mode fiber measurements which is the likely source for the ANSI
T1E1.2 committee to follow in this matter.
combination of Duty Cycle Distortion and Data Dependent Jitter.
Systematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square-wave), 2
signal.
the 50% threshold of the optical output signal using an IDLE Line
State, 125 MBd (62.5 MHz square-wave), input signal.
with the FDDI test pattern described in FDDI PMD Annex A.5.
155.52 MBd (77.5 MHz square-wave) input signal.
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the At the Beginning of Life (BOL)
over the specified operating temperature and voltage ranges 23
input is a 155.52 MBd, 2 - 1 PRBS data pattern with 72 “1” s and
72 “0”s inserted per the CCITT (now ITU-T) recommendation G.958
Appendix I.
Receiver data window time-width is 1.23 ns or greater for the clock
recovery circuit to operate in. The actual test data window time-
width is set to simulate the effect of worst case optical input jitter
based on the transmitter jitter values from the specification tables.
The test window time-width is HFBR-5963L 3.32 ns.
Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave,
input signal to simulate any cross-talk present between the trans-
mitter and receiver sections of the transceiver.
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following definitions. The Input
Optical Power dynamic range from the minimum level (with a
window time-width) to the maximum level is the range over which
the receiver is guaranteed to provide output data with a Bit Error
Rate (BER) better than or equal to 2.5 x 10
Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle
base-line wander effect of 50 kHz. This sequence causes a near worst
case condition for inter-symbol interference.
at mid-symbol. This worst case window time-width is the minimum
allowed eye-opening presented to the FDDI PHY PM_Data indica-
tion input (PHY input) per the example in FDDI PMD Annex E. This
minimum window time-width of 2.13 ns is based upon the worst
case FDDI PMD Active Input Interface optical conditions for peak-
to-peak DCD (1.0 ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the
receiver.
23
-1 psuedorandom data pattern input
-10
.
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5
16a. All conditions of Note 15a apply except that the measurement is
16b. All conditions of Note 15b apply except that the measurement is
17a. Systematic Jitter contributed by the receiver is defined as the com-
17b. Duty Cycle Distortion contributed by the receiver is measured at
17c. Data Dependent Jitter contributed by the receiver is specified with
18a. Random Jitter contributed by the receiver is specified with a 155.52
18b. Random Jitter contributed by the receiver is specified with an IDLE
19. This value is measured during the transition from low to high levels
20. This value is measured during the transition from high to low levels
21. The Signal Detect output shall be asserted within 100 us after a step
22. Signal detect output shall be de-asserted within 100 µs after a step
23. The HFBR-5963L transceiver complies with the requirements for the
To test a receiver with the worst case FDDI PMD Active Input jitter
condition requires exacting control over DCD, DDJ and RJ jitter
components that is difficult to implement with production test
equipment. The receiver can be equivalently tested to the worst case
FDDI PMD input jitter conditions and meet the minimum output
data window time-width of 2.13 ns. This is accomplished by using
a nearly ideal input optical signal (no DCD, insignificant DDJ and
RJ) and measuring for a wider window time-width of 4.6 ns. This is
possible due to the cumulative effect of jitter components through
their superposition (DCD and DDJ are directly additive and RJ com-
ponents are rms additive). Specifically, when a nearly ideal input
optical test signal is used and the maximum receiver peak-to-peak
jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns)
exist, the minimum window time-width becomes 8.0 ns -0.4 ns - 1.0
ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider window
time-width of 4.6 ns guarantees the FDDI PMD Annex E minimum
window time-width of 2.13 ns under worst case input jitter condi-
tions to the Avago receiver.
MHz square-wave), input signal to simulate any cross-talk present
between the transmitter and receiver sections of the transceiver.
made at the center of the symbol with no window time- width.
made at the center of the symbol with no window time-width.
bination of Duty Cycle Distortion and Data Dependent Jitter. Sys-
tematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square- wave), 2
signal.
the 50% threshold of the electrical output signal using an IDLE Line
State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is -20 dBm average.
the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The
input optical power level is -20 dBm average.
MBd (77.5 MHz square- wave) input signal.
Line State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is at maximum “P
formation - Transceiver Jitter Section for further information.
of input optical power.
of input optical power. At Signal Detect Deassert, the receiver
outputs Data Out and Data Out Bar go to steady PECL levels High
and Low respectively.
increase of the Input Optical Power.
decrease in the Input Optical Power. At Signal Detect Deassert, the
receiver outputs Data Out and Data Out Bar go to steady PECL levels
High and Low respectively.
trade-offs between center wavelength, spectral width, and rise/fall
times shown in Figure 7. This figure is derived from the FDDI PMD
standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the de-
scription in ANSI T1E1.2 Revision 3. The interpretation of this figure
is that values of Center Wavelength and Spectral Width must lie
along the appropriate Optical Rise/Fall Time curve.
23
- 1 psuedorandom data pattern input
IN Min.
(W)”. See Application In-