591-2304-013F Dialight, 591-2304-013F Datasheet - Page 21
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591-2304-013F
Manufacturer Part Number
591-2304-013F
Description
LED GREEN PRISM/CBI 570NM SMD
Manufacturer
Dialight
Series
Prism®, CBI®r
Specifications of 591-2304-013F
Color
Green
Voltage Rating
1.8V
Current
20mA
Lens Style/size
Round, 2.84mm
Configuration
Single
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lens Type
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Other names
350-2316-2
Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-57344 Rev. *A
Parameter
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
t
t
PLL Timing
t
t
t
POWER
CYC
KH
KL
KHKH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
QVLD
KC Var
KC lock
KC Reset
23. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
24. This part has an internal voltage regulator; t
25. These parameters are extrapolated from the input timing parameters (t
26. t
27. At any voltage and temperature t
28. t
29. Hold to >V
Cypress
operated and outputs data with the output timings of that frequency range.
design and are not tested in production.
CHZ
QVLD
, t
CLZ
specification is applicable for both rising and falling edges of QVLD signal.
are specified with a load capacitance of 5 pF as in (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IH
Consortium
KHKH
KHKL
KLKH
KHKH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
CQHQVLD
KC Var
KC lock
KC Reset
Parameter
or <V
IL
.
V
K Clock Cycle Time
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
K Clock Rise to K Clock Rise
(rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to K Clock Rise (LD, R/W)
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS
D
Address Hold after K Clock Rise
Control Hold after K Clock Rise (LD, R/W)
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS
D
K/K Clock Rise to Data Valid
Data Output Hold after Output K/K Clock Rise
(Active to Active)
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (K/K) Rise to High Z
(Active to High Z)
Clock (K/K) Rise to Low Z
Echo Clock High to QVLD Valid
Clock Phase Jitter
PLL Lock Time (K)
K Static to PLL Reset
DD
[22, 23]
[X:0]
[X:0]
CHZ
(Typical) to the First Access
Hold after Clock (K/K) Rise
Setup to Clock (K/K) Rise
is less than t
0
0
, BWS
, BWS
POWER
CLZ
is the time that the power is supplied above V
Description
[26, 27]
1
1
, BWS
, BWS
and t
[29]
CHZ
2
2
[26, 27]
, BWS
, BWS
less than t
[25]
[25]
AC Test Loads and
[28]
[24]
CYC
3
3
)
)
CO
/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
.
Waveforms. Transition is measured ±100 mV from steady-state voltage.
0.655
0.655
-0.45
-0.45
-0.15
-0.45
-0.15 0.15 -0.15 0.15 -0.15 0.15 -0.20 0.20
1.81
0.77
0.23
0.23
0.18
0.18
0.23
0.23
0.18
0.18
Min Max Min Max Min Max Min Max
0.4
0.4
550 MHz
20
30
1
–
–
–
–
–
DD
0.45
0.45
0.15
0.45
0.15
min initially before a read or write operation can be initiated.
8.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-0.45
-0.45
-0.15
-0.45
0.85
0.25
0.25
0.20
0.20
0.25
0.25
0.20
0.20
0.75
0.75
2.0
0.4
0.4
500 MHz
20
30
1
–
–
–
–
–
0.45
0.45
0.15
0.45
0.15
8.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.275
0.275
0.275
0.275
-0.45
-0.45
-0.45
-0.15
0.94
0.22
0.22
0.22
0.22
0.85
0.85
2.2
0.4
0.4
450 MHz
20
30
1
–
–
–
–
–
CY7C21701KV18
0.45
0.45
0.15
0.45
0.15
8.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-0.45
-0.45
-0.20
-0.45
1.06
0.28
0.28
0.28
0.28
1.00
1.00
2.5
0.4
0.4
0.4
0.4
0.4
0.4
400 MHz
20
30
1
–
–
–
–
–
Page 21 of 24
0.45
0.45
0.20
0.45
0.20
8.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
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