LMZ14203TZ-ADJ/NOPB National Semiconductor, LMZ14203TZ-ADJ/NOPB Datasheet - Page 9

• Manufacturer Part Number: LMZ14203TZ-ADJ/NOPB
• Description: IC BUCK SYNC ADJ 3A TO-PMOD-7
• Manufacturer: National Semiconductor
• Series: SIMPLE SWITCHER®r
• Type: Point of Load (POL) Non-Isolated with UVLOr

Specifications of LMZ14203TZ-ADJ/NOPB

• Output: 0.8 ~ 6 V
• Number Of Outputs: 1
• Power (watts): 18W
• Mounting Type: Surface Mount
• Voltage - Input: 6 ~ 42 V
• Package / Case: TO-PMOD-7, Power Module
• 1st Output: 0.8 ~ 6 VDC @ 3A
• Size / Dimension: 0.40" L x 0.54" W x 0.18" H (10.16mm x 13.77mm x 4.57mm)
• Power (watts) - Rated: 18W
• Operating Temperature: -40°C ~ 125°C
• Efficiency: 90%
• Approvals: EN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -
• Other names: LMZ14203TZ-ADJTR

Application Block Diagram
COT Control Circuit Overview
Constant On Time control is based on a comparator and an
on-time one shot, with the output voltage feedback compared
with an internal 0.8V reference. If the feedback voltage is be-
low the reference, the main MOSFET is turned on for a fixed
on-time determined by a programming resistor R
connected to V
input supply voltage. Following this on-time, the main MOS-
FET remains off for a minimum of 260 ns. If the voltage on the
feedback pin falls below the reference level again the on-time
cycle is repeated. Regulation is achieved in this manner.
Design Steps for the LMZ14203
Application
The LMZ14203 is fully supported by Webench® and offers
the following: Component selection, electrical and thermal
simulations as well as the build-it board for a reduction in de-
sign time. The following list of steps can be used to manually
design the LMZ14203 application.
• Select minimum operating V
• Program V
• Program turn-on time with soft-start capacitor selection
• Select C
• Select C
• Set operating frequency with R
• Determine module dissipation
• Layout PCB for required thermal performance
ENABLE DIVIDER, R
The enable input provides a precise 1.18V band-gap rising
threshold to allow direct logic drive or connection to a voltage
divider from a higher enable voltage such as V
input also incorporates 90 mV (typ) of hysteresis resulting in
a falling threshold of 1.09V. The maximum recommended
voltage into the EN pin is 6.5V. For applications where the
midpoint of the enable divider exceeds 6.5V, a small zener
can be added to limit this voltage.
O
IN
O
with divider resistor selection
IN
such that on-time is reduced with increasing
ENT
AND R
IN
with enable divider resistors
ON
ENB
SELECTION
IN
. The enable
ON
. R
ON
is
9
The function of this resistive divider is to allow the designer to
choose an input voltage below which the circuit will be dis-
abled. This implements the feature of programmable under
voltage lockout. This is often used in battery powered systems
to prevent deep discharge of the system battery. It is also
useful in system designs for sequencing of output rails or to
prevent early turn-on of the supply as the main input voltage
rail rises at power-up. Applying the enable divider to the main
input rail is often done in the case of higher input voltage sys-
tems such as 24V AC/DC systems where a lower boundary
of operation should be established. In the case of sequencing
supplies, the divider is connected to a rail that becomes active
earlier in the power-up cycle than the LMZ14203 output rail.
The two resistors should be chosen based on the following
ratio:
R
The LMZ14203 demonstration and evaluation boards use
11.8kΩ for R
LO of 8V. This divider presents 6.25V to the EN input when
the divider input is raised to 42V.
The EN pin is internally pulled up to VIN and can be left float-
ing for always-on operation.
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors
connected between V
vider is connected to the FB input. The voltage at FB is
compared to a 0.8V internal reference. In normal operation
an on-time cycle is initiated when the voltage on the FB pin
falls below 0.8V. The main MOSFET on-time cycle causes the
output voltage to rise and the voltage at the FB to exceed
0.8V. As long as the voltage at FB is above 0.8V, on-time
cycles will not occur.
The regulated output voltage determined by the external di-
vider resistors R
V
Rearranging terms; the ratio of the feedback resistors for a
desired output voltage is:
R
O
ENT
FBT
= 0.8V * (1 + R
/ R
/ R
FBB
ENB
= (V
= (V
ENB
FBT
O
and 68.1kΩ for R
IN UVLO
/ 0.8V) - 1 (3)
FBT
and R
O
/ R
/ 1.18V) – 1 (1)
and ground. The midpoint of the di-
FBB
FBB
) (2)
is:
ENT
30107008
resulting in a rising UV-
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