Z8F64230100ZDF Zilog, Z8F64230100ZDF Datasheet - Page 147
Z8F64230100ZDF
Manufacturer Part Number
Z8F64230100ZDF
Description
ADAPTER ICE Z8 ENCORE 64K 80QFP
Manufacturer
Zilog
Specifications of Z8F64230100ZDF
Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3405
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Table 63. SPI Data Register (SPIDATA)
SPI Control Register Definitions
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
SPI Data Register
SPI Control Register
7
The SPI Data register
(receive) data. Reads from the SPI Data register always return the current contents of the
8-bit shift register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error Flag, OVR, is set in the SPI Status register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
register), the transmit character must be left justified in the SPI Data register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be writ-
ten to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
DATA—Data
Transmit and/or receive data.
The SPI Control register (see
receive operations.
6
(Table
5
63) stores both the outgoing (transmit) data and the incoming
Table 64
4
on page 134) configures the SPI for transmit and
DATA
F60H
R/W
X
3
Z8 Encore! XP
2
Product Specification
Serial Peripheral Interface
1
®
F64XX Series
0
133
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