VDIP2 FTDI, Future Technology Devices International Ltd, VDIP2 Datasheet - Page 22

• Manufacturer Part Number: VDIP2
• Description: MOD MCU-USB HOST CTLR 40-DIP
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculumr

Specifications of VDIP2

• Main Purpose: Interface, USB 2.0 Host/Controller
• Embedded: Yes, ASIC
• Utilized Ic / Part: VNC1L-1A
• Primary Attributes: Dual A-Type Connector, UART / Parallel FIFO / SPI Interfaces
• Secondary Attributes: Firmware Update via USB Flash Drive or UART, Traffic LEDs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1002

Document Reference No.: FT_000017
VDIP2 Vinculum VNC1L Module Datasheet Version 1.0
Clearance No.: FTDI# 145
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Appendix B – List of Figures and Tables
List of Figures
Figure 1.1- VDIP2 ......................................................................................................................... 1
Figure 3.1 – VDIP2 Module Pin Out (Top View) ................................................................................. 4
Figure 3.2 – VDIP2 On-Board Jumper Pin Configuration. ................................................................... 7
Figure 3.3 – SPI Slave Data Read Cycle. ........................................................................................ 10
Figure 3.4 – SPI Slave Data Write Cycle. ....................................................................................... 11
Figure 3.5 – SPI Slave Data Timing Diagrams................................................................................. 12
Figure 3.6 - FIFO Read Cycle. ....................................................................................................... 14
Figure 3.7 - FIFO Write Cycle. ...................................................................................................... 15
Figure 5.1 VDIP2 Dimensions (Top View) ....................................................................................... 17
Figure 5.2 VDIP2 Dimensions (Side View) ...................................................................................... 17
Figure 7.1 - Schematic Diagram ................................................................................................... 18
List of Tables
Table 3.1 - Pin Signal Descriptions .................................................................................................. 5
Table 3.2 – VDIP2 Port Selection Jumper Pins .................................................................................. 7
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Slave Interface ...................................... 10
Table 3.6 - SPI Slave Data Timing ................................................................................................ 12
Table 3.7 - SPI Slave Status Register (ADD=’1’) ............................................................................. 12
Table 3.8 - Default Interface I/O Pin Configuration Option – Paralle FIFO Interface ............................ 13
Table 3.9 FIFO Read Cycle Timing ................................................................................................. 14
Table 3.10 - FIFO Write Cycle Timing ............................................................................................ 15
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