ATA6612-EK Atmel, ATA6612-EK Datasheet - Page 64
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ATA6612-EK
Manufacturer Part Number
ATA6612-EK
Description
BOARD DEMO LIN-MCM FOR ATA6612
Manufacturer
Atmel
Specifications of ATA6612-EK
Main Purpose
Interface, LIN + MCU
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ATA6612
Primary Attributes
LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
Secondary Attributes
8 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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6.7.3
6.7.4
6.7.5
64
Atmel ATA6612/ATA6613
ADC Noise Reduction Mode
Power-down Mode
Power-save Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the
2-wire Serial Interface address watch, Timer/Counter2, and the Watchdog to continue operat-
ing (if enabled). This sleep mode basically halts clk
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements.
If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from
the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a
Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on
INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction
mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external inter-
rupts, the 2-wire Serial Interface address watch, and the Watchdog continue operating (if
enabled). Only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a
Brown-out Reset, a 2-wire Serial Interface address match, an external level interrupt on INT0
or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all
generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to
on page 108
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define
the Reset Time-out period, as described in
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception.
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from
either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding
Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in
SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save
mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is
stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source
is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this
clock is only available for Timer/Counter2.
for details.
“Clock Sources” on page
I/O
, clk
CPU
, and clk
52.
FLASH
“External Interrupts”
, while allowing the
9111H–AUTO–01/11
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