DC1459A Linear Technology, DC1459A Datasheet - Page 2

• Manufacturer Part Number: DC1459A
• Description: BOARD EVALUATION FOR LTC3588
• Manufacturer: Linear Technology

Specifications of DC1459A

• Main Purpose: Power Management, Renewable Energy
• Embedded: No
• Utilized Ic / Part: LTC3588
• Primary Attributes: Pin Selectable Voltage, 1.8V, 2.5V, 3.3V, 3.6V
• Secondary Attributes: Up to 100mA Output
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the voltage on V
threshold the buck converter is enabled and charge
is transferred from the input capacitor to the output
capacitor. A wide (~1V) UVLO hysteresis window is
employed with a lower threshold approximately
200mV above the selected regulated output voltage
to prevent short cycling during buck power-up.
When the input capacitor voltage is depleted below
the UVLO falling threshold the buck converter is dis-
abled.
Two internal rails, CAP and V
V
low side NMOS of the buck converter, respectively.
Additionally the V
put voltage select bits D0 and D1. The V
gulated at 4.8V above GND while the CAP rail is regu-
lated at 4.8V below V
used as external rails. Capacitors should be con-
nected to the CAP and V
reservoirs for driving the buck switches.
The buck regulator uses a hysteretic voltage algo-
rithm to control the output through internal feedback
from the V
an output capacitor through an inductor to a value
slightly higher than the regulation point. It does this
QUICK START PROCEDURE
Using short twisted pair leads for any power con-
nections, with all loads and power supplies off, refer
to Figure 1 for the proper measurement and equip-
ment setup.
Follow the procedure below:
2
IN
1. Before connecting PS1 to the DC1459A, PS1
and are used to drive the high side PMOS and
must have its current limit set to 50mA. For
most power supplies with a current limit ad-
justment feature the procedure to set the cur-
rent limit is as follows. Turn the voltage and
current adjustment to minimum. Short the
OUT
sense pin. The buck converter charges
IN2
rail serves as logic high for out-
IN
IN
. These are not intended to be
IN2
crosses the UVLO rising
pins to serve as energy
IN2
, are generated from
IN2
rail is re-
by ramping the inductor current up to 250mA
through an internal PMOS switch and then ramping it
down to 0mA through an internal NMOS switch.
When the buck brings the output voltage into regula-
tion the converter enters a low quiescent current
sleep state that monitors the output voltage with a
sleep comparator. During this operating mode load
current is provided by the buck output capacitor.
When the output voltage falls below the regulation
point the buck regulator wakes up and the cycle re-
peats. This hysteretic method of providing a regu-
lated output reduces losses associated with FET
switching and maintains an output at light loads. The
buck delivers a minimum of 100mA average load
current when it is switching.
A power good comparator produces a logic high ref-
erenced to V
converter reaches the programmed V
that the output is in regulation. The PGOOD pin will
remain high until V
regulated voltage.
2. Initial Jumper, PS and LOAD 1settings:
3. Connect PS1 to the VIN Terminals, then turn
outputs terminals and turn the voltage ad-
justment to maximum. Adjust the current
limit to 50mA. Turn the voltage adjustment to
minimum. The power supply is now current
limited to 50mA.
JP1 = 0
JP2 = 0
on PS1 and slowly increase voltage to 2.0V
OUT
on the PGOOD pin the first time the
OUT
LTC3588EMSE-1
falls to 92% of the desired
PS1 = OFF
LOAD1 = OFF
OUT
, signaling