W681360DK Nuvoton Technology Corporation of America, W681360DK Datasheet - Page 7

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W681360DK

Manufacturer Part Number
W681360DK
Description
KIT DEVELOPMENT FOR W681360
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W681360DK

Main Purpose
Audio, CODEC
Utilized Ic / Part
W681360
Lead Free Status / RoHS Status
Lead free by exemption / Not applicable
Secondary Attributes
-
Embedded
-
Primary Attributes
-
ON
OFF
ON
OFF
Chapter - 2
Hardware Description
Clock Generator:
All the necessary clock rates such as Frame Sync, Bit Clock and the 256 KHz for the
W681xxxDK evaluation system are driven from a single 4.096 MHz crystal oscillator.
Frame Sync:
The Frame Sync is generated on the W681xxxDK evaluation board. J19 and J20 (SW5)
control the FSR (Frame Sync Receive) and FSX (Frame Sync Transmit) routing.
Enabling these jumpers also routes the signal to the 40-pin header (J11).
Setting Dip Switches:
Switch SW2 selects the width of the Frame Sync. The pulse width is set as a number of
BCLKs. The following number of BCLKs for Frame Sync can be set with SW2.
• 1-2-3-4-5-6-7-8
The Dip-Switch SW2 configurations are:
WECA
2727 N First Street, San Jose CA 95134
1
Frame Sync = 5 BCLK
Frame Sync = 7 BCLK
8
OFF
OFF
ON
ON
Frame Sync = 4 BCLK
Frame Sync = 6 BCLK
W681xxxDK
7

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