CP2400AB Silicon Laboratories Inc, CP2400AB Datasheet - Page 104

• Manufacturer Part Number: CP2400AB
• Description: BOARD EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400AB

• Main Purpose: LCD Development
• Embedded: No
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Accessories
• Core Processor: CP2400
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: CP2400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1857

CP2400/1/2/3
15. SMBus Interface
The SMBus I/O interface is a two-wire, bi-directional serial bus that can be used to access the internal registers
and memory on CP2401/3 devices. The SMBus is compliant with the System Management Bus Specification,
version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are
byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be
transferred at up to 1/20th of the system clock (this can be faster than allowed by the SMBus specification,
depending on the system clock used). A method of extending the clock-low duration is available to accommodate
devices with different speed capabilities on the same bus.
15.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
15.2. SMBus Configuration
Figure 15.1 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between
3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial
clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or
similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the
SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of
devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and
1000 ns, respectively.
104
1. The I
2. The I
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
VDD = 5 V
2
2
C-Bus and How to Use It (including specifications), Philips Semiconductor.
C-Bus Specification—Version 2.0, Philips Semiconductor.
Figure 15.1. Typical SMBus Configuration
VDD = 3 V
Master
Device
Rev. 1.0
VDD = 5 V
Device 1
Slave
VDD = 3 V
Device 2
Slave
SDA
SCL