SD005EVK National Semiconductor, SD005EVK Datasheet - Page 6
SD005EVK
Manufacturer Part Number
SD005EVK
Description
BOARD EVALUATION CLC005
Manufacturer
National Semiconductor
Datasheet
1.CLC005AJENOPB.pdf
(12 pages)
Specifications of SD005EVK
Design Resources
SD005EVK Schematic
Main Purpose
Interface, Digital Cable Driver
Utilized Ic / Part
CLC005
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Not Compliant
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Operation
OUTPUT AMPLITUDE ADJUSTMENT
The high and low output levels of the CLC005 are set by a
circuit shown simplified in Figure 8 . Output high and low lev-
els may be set independently with external resistor networks
connected between R
power supplies. The resistor networks affect the high and
low output levels by changing the internally generated bias
voltages, V
are V
R
components which determine output voltage levels have ac-
curate ratios, their absolute values may be controlled only
within about
justment, output voltages are well controlled. A final design
should accommodate the variation in externally set output
voltages due to the CLC005’s part-to-part and external com-
ponent tolerances.
Output voltage swing may be reduced with the circuit shown
in Figure 9 . A single resistance chosen with the aid of the
graph, Figure 10 , is connected between pins 3 and 4. Output
voltage swing may be increased with the circuit of Figure 11 .
Figure 12 is used to estimate a value for resistor R. Note that
both of these circuits and the accompanying graphs assume
that the CLC005 is loaded with the standard 150 . Be aware
that output loading will affect the output swing and the high
EXT-H
CC
and R
−1.7V and V
H
±
and V
EXT-L
15% of nominal. Even so, without external ad-
(Continued)
are left unconnected. Though the internal
L
. The nominal high and low output levels
CC
EXT-H
−3.7V, respectively, when the pins
(pin 3), R
FIGURE 7. Differential Input DC Coupled Output
EXT-L
(pin 4) and the
6
and low levels. It may be necessary to empirically select re-
sistances used to set output levels when the D.C. loading on
the CLC005 differs appreciably from 150 .
FIGURE 8. Equivalent Bias Generation Circuit
DS100144-10
DS100144-11