SD006EVK National Semiconductor, SD006EVK Datasheet - Page 6

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SD006EVK

Manufacturer Part Number
SD006EVK
Description
BOARD EVALUATION CLC006
Manufacturer
National Semiconductor
Datasheet

Specifications of SD006EVK

Design Resources
SD006EVK Schematic
Main Purpose
Interface, Digital Cable Driver
Utilized Ic / Part
CLC006
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
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OUTPUT AMPLITUDE ADJUSTMENT
The high and low output levels of the CLC006 are set by a
circuit shown simplified in Figure 8. Output high and low levels
may be set independently with external resistor networks
connected between R
power supplies. The resistor networks affect the high and low
output levels by changing the internally generated bias volt-
ages, V
V
and R
nents which determine output voltage levels have accurate
ratios, their absolute values may be controlled only within
about ±15% of nominal. Even so, without external adjustment,
CC
−1.7V and V
EXT-L
H
and V
are left unconnected. Though the internal compo-
L
. The nominal high and low output levels are
CC
−3.3V, respectively, when the pins R
EXT-H
(pin 3), R
FIGURE 7. Differential Input DC Coupled Output
EXT-L
(pin 4) and the
FIGURE 6. Output Stage
EXT-H
6
output voltages are well controlled. A final design should ac-
commodate the variation in externally set output voltages due
to the CLC006’s part-to-part and external component toler-
ances.
Output voltage swing may be reduced with the circuit shown
in Figure 9. A single resistance chosen with the aid of the
graph, Figure 10, is connected between pins 3 and 4. Output
voltage swing may be increased with the circuit of Figure 11.
Figure 12 is used to estimate a value for resistor R. Note that
both of these circuits and the accompanying graphs assume
that the CLC006 is loaded with the standard 150Ω. Be aware
10008409
10008410

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