DP83848K-MAU-EK National Semiconductor, DP83848K-MAU-EK Datasheet - Page 4

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DP83848K-MAU-EK

Manufacturer Part Number
DP83848K-MAU-EK
Description
BOARD EVALUATION DP83848K
Manufacturer
National Semiconductor
Datasheets

Specifications of DP83848K-MAU-EK

Main Purpose
Interface, Ethernet
Utilized Ic / Part
DP83848K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Not Compliant
PCB Physical Layout requirements / Considerations
MAU Interface requirements
Software
Additional information
National Semiconductor Corporation
www.national.com
FR4 material
Trace impedance will be ensured by design:
Trace length matching between differential pairs not required
Trace space will be 0.007”/0.008” minimum
Uniform supply & ground plane
Combination of through-hole and surface mount technology
Target size 2.05” (height), 1.5” (length)
4 layers
Silk screen on two sides
System interface will be via the MII connector, and MII header
RJ-45 for network connection
No device specific software is required for this board
National does provide the integrity utility; a diagnostic and configuration package at
www.national.com/appinfo/networks/ethernet_utility.html
Updated versions of the included material, related material can be found by going to
ethernet.national.com
http://www.national.com/appinfo/networks/webench/dp83848.html
o
o
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Trace symmetry within differential pair (+/- 0.5”)
Differential impedance 100 ohms, +/- 5%
Adjacent differential pairs spacing > 2X distance within a differential pair, to
minimize cross-talk and EMI
or directly to design resources at
MDIO parallel port
connection
MII
PHYAD
strap
MAU Block Diagram
DP83848K
LED_CFG
Strap
25MHz
Xtal
MDIX_EN
strap
Integrated
Magnetic
RJ-45

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