SI3225DC0-EVB Silicon Laboratories Inc, SI3225DC0-EVB Datasheet - Page 18

• Manufacturer Part Number: SI3225DC0-EVB
• Description: DAUGHTER CARD W/SI3200 INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3225DC0-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3225
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3220/25 Si3200/02
18
Table 13. Switching Characteristics—PCM Highway Interface
(V
Parameter
PCLK Period
Valid PCLK Inputs
FSYNC Period
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX
Transition
Delay Time, PCLK Rise to DTX
Tristate
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
Notes:
DD
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
, V
DD1
3
– V
DD4
2
=
3.13 to 5.25 V, T
A
=
0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, C
Symbol
t
t
t
t
t
jitter
t
t
t
t
t
su1
su2
t
wfs
t
dty
d1
d2
d3
h1
h2
t
t
fs
p
r
f
Rev. 1.3
Conditions
Test
Min
122
t
40
25
20
25
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
p
/2
1
IH –
V
I/O –
1.024
1.536
1.544
2.048
4.096
8.192
Typ
256
512
768
125
50
—
—
—
—
—
—
—
—
—
—
—
—
0.4 V, V
1
L
=
20 pF)
IL
125 µs–t
=
Max
3906
±120
0.4 V.
60
25
25
20
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
p
Units
MHz
MHz
MHz
MHz
MHz
MHz
kHz
kHz
kHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%