SI3210PPQ1-EVB Silicon Laboratories Inc, SI3210PPQ1-EVB Datasheet - Page 136

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SI3210PPQ1-EVB

Manufacturer Part Number
SI3210PPQ1-EVB
Description
BOARD EVAL W/SI3201 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets

Specifications of SI3210PPQ1-EVB

Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3210
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Si3210/Si3211
8.2.2. PCB Land Pattern: 38-Pin TSSOP
Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values
for the dimensions shown in the illustration.
136
Dimension
C1
E
X1
Y1
Notes:
Figure 36. TSSOP-38 PCB Land Pattern Drawing
1. All dimensions shown are in millimeters (mm) unless
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition
5. The recommended card reflow profile is per the JEDEC/IPC
otherwise noted.
(MMC). Least Material Condition (LMC) is calculated based
on a Fabirication Allowance of 0.05mm.
J-STD-020 specification for Small Body Components.
Table 51. PCB Land Pattern Dimensions
Pad Column Spacing
Pad Row Pitch
Pad Length
Pad Width
Feature
Rev. 1.5
(mm)
5.80
0.50
0.30
1.45

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