SI3210PPQ1-EVB Silicon Laboratories Inc, SI3210PPQ1-EVB Datasheet - Page 71
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SI3210PPQ1-EVB
Manufacturer Part Number
SI3210PPQ1-EVB
Description
BOARD EVAL W/SI3201 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets
1.SI3201-KS.pdf
(138 pages)
2.SI3210PPQX-EVB.pdf
(40 pages)
3.SI3210MPPQX-EVB.pdf
(146 pages)
Specifications of SI3210PPQ1-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3210
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register 10. Two-Wire Impedance Synthesis Control
Reset settings = 0000_1000
Name
Bit
7:6
5:4
2:0
Type
3
Bit
Reserved
TISS[2:0]
CLC[1:0]
Name
TISE
D7
Read returns zero.
Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
Two-Wire Impedance Synthesis Selection.
000 = 600
001 = 900
010 = 600 + 2.16 µF
011 = 900 + 2.16 µF
100 = CTR21 (270 + 750 || 150 nF)
101 = Australia/New Zealand #1 (220 + 820 || 120 nF)
110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF)
111 = New Zealand #2 (370 + 620 || 310 nF)
D6
D5
CLC[1:0]
R/W
Rev. 1.45
D4
Function
TISE
R/W
D3
D2
Si3210/Si3211
TISS[2:0]
R/W
D1
D0
71
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