SI3056PPT-EVB Silicon Laboratories Inc, SI3056PPT-EVB Datasheet - Page 2

• Manufacturer Part Number: SI3056PPT-EVB
• Description: BOARD EVAL FOR DAA SI3056/SI3018
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3056PPT-EVB

• Main Purpose: Telecom, Data Acquisition Arrangement (DAA)
• Utilized Ic / Part: Si3056
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si30xxPPT-EVB
Functional Description
The Si30xxPPT-EVB provides the telecommunications
system engineer an easy way to evaluate the Si30xx
solution. Silicon Labs’ DAAs are integrated direct
access arrangements that provide a digital, low-cost,
solid-state interface to worldwide telephone lines.
Through the patented ISOcap technology, the Si30xx
eliminates the need for an analog frond end (AFE), an
isolation transformer, relays, opto-isolators, and a 2 to
4-wire hybrid.
The Si30xxPPT-EVB also supports the connection of
multiple devices on an SSI interface. The evaluation
board provides a straightforward means of evaluating
this feature.
The evaluation board consists of the Si30xxPPT-EVB
Si-LINK (mother) board and the Si30xxDC_EVB
daughter card. A custom ribbon cable is also provided
to connect to the parallel port of a PC. Contact a Silicon
Laboratories representative for more information.
Motherboard-Daughter Card Connection
The Si30xxDC-EVB connects to the Si30xxPPT-EVB
through two sockets: JP1 and JP2. JP1 is a 3x8 socket
connection to the digital signals of the DSP-side chip, as
well as to the analog AOUT pin. In addition, a 3.3 V
regulated supply is routed to this socket and supplies
the power to the digital-side device. JP1 of the daughter
card connects to JP2 of the Si30xxPPT-EVB. JP2 is a
2x5 socket connection from the TIP and RING and
chassis ground of the line interface to the line-side
device. JP2 of the Si30xx DC-EVB connects to JP1 of
the Si30xx PPT EVB.
Power Supply
Power is supplied to the EVB by means of J3 or J4. J3
is a euroblock header that allows for connection to a
bench power supply. J4 is a 2.1 mm power jack that
allows the use of a wall transformer. A 9 V supply/
300 mA is typically used, but the onboard voltage
regulator also works with a dc voltage between 7.5 V
and 20 V. A diode bridge is used to correct polarity. The
on-board regulator, U7, provides 5 V to the call progress
circuit, the on-board oscillator, and other boards daisy
chained to the Si30xxPPT-EVB. This 5 V is further
regulated to 3.3 V to power the daughter card and the
input/output ports of the FPGA. A third regulator
provides 2.5 V for the core voltage of the FPGA.
Clock Generation
The Si30xx requires an MCLK input. An on-board
oscillator (Y1) is used by the FPGA to clock all the
subsystems as well as generate and provide the master
2
Preliminary Rev. 1.0
clock to the DAA. The FPGA is designed to use a
18.432 MHz oscillator (included with the board).
Optional Call Progress Speaker
The AOUT pin of the digital-side device provides a call
monitoring feature. U3 provides 25 dB of signal gain on
this output. The AOUT pin has an output impedance of
10 kW. R9 and R10 form a voltage divider that provides
a gain of –24.4 dB. This divider is necessary so the
LM386, which is operating from a +5 V supply, is not
overdriven. The LM386 is a cost-effective low-power
amplifier capable of driving many different buzzers or
speakers. In the case of cascaded evaluation boards,
the AOUT signal is local to each board.
Reset Circuit
The Si30xx requires an active low pulse on RESET
following powerup and whenever all registers need to
be reset. For development purposes, the Si30xxPPT-
EVB includes a reset push button, SW1, that is used by
the FPGA to generate a reset pulse of the DAA.
If multiple boards are cascaded together, the reset
signal should be generated by the master board. Using
the SW1 pushbutton on slave boards does not reset
that slave board.
Serial Modes
The Si30xx supports several different serial modes for a
glueless interface to many standard DSP and ASIC
serial ports. The serial mode of the Si30xx can be
selected by JP3 and JP4.
Line Connection
J1 is provided to connect the EVB to a standard RJ-11
connector. The system cannot execute an off-hook
command without the phone line connected. This
condition can be detected by examining the FDT bit of
register 12 or by simply observing that there is no dial
tone on the DSP or ASIC.
PC Parallel Port
JP13 connects through the Silicon Labs custom ribbon
cable to the parallel port of the PC. The parallel port
connection allows the designer to read and write the
DAA register using the evaluation software included
with the Si30xxPPT-EVB.