LMX2485E EVAL National Semiconductor, LMX2485E EVAL Datasheet
LMX2485E EVAL
Specifications of LMX2485E EVAL
Related parts for LMX2485E EVAL
LMX2485E EVAL Summary of contents
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... Applications ■ Cellular phones and base stations CDMA, WCDMA, GSM/GPRS, TDMA, EDGE, PDC ■ Direct digital modulation applications Functional Block Diagram PLLatinum ™ trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation ■ Satellite and cable TV tuners ■ WLAN Standards Features Quadruple Modulus Prescalers for Lower Divide Ratios ■ ...
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Connection Diagram Pin Descriptions Pin # Pin Name I/O 0 GND - 1 CPoutRF O 2 GND - 3 VddRF1 - 4 FinRF I 5 FinRF DATA I 8 CLK I 9 VddRF2 - 10 ...
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Absolute Maximum Ratings Parameter Power Supply Voltage Voltage on any pin with GND = 0V Storage Temperature Range Lead Temperature (Solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage (Note 1) Operating Temperature Note 1: “Absolute Maximum Ratings” indicate ...
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Symbol Parameter RF Charge Pump Sink I SINK Current CPoutRF (Note 5) RF Charge Pump TRI- I TRI STATE Current CPoutRF Magnitude Magnitude Sink | I %MIS | CPoutRF vs. CP Source Mismatch Magnitude ...
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Symbol Parameter PHASE NOISE RF Synthesizer L RF Normalized Phase Noise F1Hz Contribution (Note 7) IF Synthesizer L IF Normalized Phase Noise F1Hz Contribution DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF) V High-Level Input Voltage IH V Low-Level ...
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Typical Performance Characteristics : Sensitivity www.national.com (Note 8) RF PLL Fin Sensitivity T = 25°C, RF_P = PLL Fin Sensitivity V = 3.0 V, RF_P = 20087745 20087746 ...
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IF PLL Fin Sensitivity T = 25°C, IF_P = PLL Fin Sensitivity V = 3.0 V, IF_P = 20087747 20087748 www.national.com ...
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OSCin Sensitivity T = 25°C, OSC_2X = 0 A OSCin Sensitivity V = 3.0 V, OSC_2X = 20087749 20087756 ...
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OSCin Sensitivity T = 25°C, OSC_2X = 1 A OSCin Sensitivity V = 3.0 V, OSC_2X = 20087773 20087774 www.national.com ...
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Typical Performance Characteristic : FinRF Input Impedance Frequency (MHz) 50 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 ...
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Typical Performance Characteristic : FinIF Input Impedance Frequency (MHz 100 200 300 400 500 600 700 800 900 1000 FinIF Input Impedance Real (Ohms) 583 530 499 426 384 347 310 276 244 216 192 173 11 (Note ...
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Typical Performance Characteristic : OSCin Input Impedance Frequency (MHz) Real 5 1730 10 846 20 466 30 351 40 316 50 278 60 261 70 252 80 239 90 234 100 230 110 225 120 219 130 214 140 208 ...
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Typical Performance Characteristics : Currents (Note 8) Power Supply Current CE = High Power Supply Current CE = LOW 13 20087759 20087761 www.national.com ...
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RF PLL Charge Pump Current V = 3.0 Volts CC IF PLL Charge Pump Current V = 3.0 Volts CC 14 20087767 20087765 ...
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Note 8: Typical performance characteristics do not imply any sort of guarantee. Guaranteed specifications are in the electrical characteristics section. Charge Pump Leakage RF PLL V = 3.0 Volts CC Charge Pump Leakage IF PLL V = 3.0 Volts CC ...
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Bench Test Setups Charge Pump Current Measurement Procedure The above block diagram shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current level, mismatch, and leakage measurement. In order to measure the charge ...
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Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current at V CPout I2 = Charge Pump Sink Current at V CPout I3 = Charge Pump Sink Current at V CPout I4 = Charge Pump Source Current at V ...
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Frequency Input Pin DC Blocking Capacitor OSCin 1000 pF FinRF 100 pF// 1000 pF FinIF 100 pF OSCin 1000 pF Sensitivity Measurement Procedure Sensitivity is defined as the power level limits beyond which the output of the counter being tested ...
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Input Impedance Measurement Procedure The above block diagram shows the test setup used for mea- suring the input impedance for the LMX2485. The DC block- ing capacitor used between the input SMA connector and the pin being measured must be ...
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Functional Description 1.0 GENERAL The LMX2485 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter are sup- plied external to the chip. The various blocks are described below. 1.1 TCXO, OSCILLATOR BUFFER, AND ...
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CE Pin RF_PD ATPU Bit Enabled + Write Counter Low X X High X Yes High 0 No High 1 No 1.7 DIGITAL LOCK DETECT OPERATION The RF PLL digital lock detect circuitry compares the differ- ence ...
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CYCLE SLIP REDUCTION AND FASTLOCK The LMX2485 offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that it re- quires no additional programming overhead to use them generally recommended that the charge ...
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In this case, the value for R2p is typi- cally about 80% of what it would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep the loop filter ...
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Programming Description 2.0 GENERAL PROGRAMMING INFORMATION The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter, the N counter, and the internal mode control latches. The data format of a ...
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Complete Register Map The complete register map shows all the functionality of all registers, including the last five GIS TE R DATA[19:0] ( Except for the RF_N Register, which is [22:0] ) ...
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Operation with the 8/9/12/13 Prescaler (RF_P=0) RF_N <25 25-26 27- ... . . 1023 1 1 >1023 Operation with the 16/17/20/21 Prescaler (RF_P=1) RF_N <49 49-50 51- ... . . 2039 1 1 2040-20 ...
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R1 REGISTER REGISTER RF_PD RF_P 2.2.1 RF_FD[11: PLL Fractional Denominator The function of these bits are ...
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R2 REGISTER REGISTER IF_PD 2.3.1 IF_N[18: Divider Value IF_N Counter Programming with the 8/9 Prescaler (IF_P=0) N Valu e ≤ values less than or equal to 23 are prohibited because ...
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R3 REGISTER REGISTER ACCESS[3:0] 2.4.1 IF_R[11: Divider Value For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for ...
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Re gis ter This corresponds to the following bit settings. Register Bit ...
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R4 REGISTER This register controls the conditions for the RF PLL in Fastlock. REGISTER ATPU 2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX ...
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RF_CPP -- RF PLL Charge Pump Polarity RF_CPP 0 1 2.5.4 IF_CPP -- IF PLL Charge Pump Polarity For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for ...
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DITH[1:0] -- Dithering Control Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts ...
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R5 REGISTER REGISTER RF_FD[21:12] 2.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[ the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] bits ...
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R6 REGISTER REGISTER CSR[1:0] RF_CPF[3:0] 2.7.1 RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of ...
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CSR[1: Cycle Slip Reduction CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase detector cycle slips. Note that the Fastlock charge pump current, steady state ...
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R7 REGISTER 2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4 Because the digital lock detect function is based ...
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www.national.com 38 ...
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Physical Dimensions inches (millimeters) unless otherwise noted Order Number LMX2485SQ or LMX2485ESQ for 1000 Unit Reel Order Number LMX2485SQX or LMX2485ESQX for 4500 Unit Reel Plastic Quad LLP (SQ), Bottom View NS Package Number SQA24A 39 www.national.com ...
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