SI5315-EVB Silicon Laboratories Inc, SI5315-EVB Datasheet

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SI5315-EVB

Manufacturer Part Number
SI5315-EVB
Description
BOARD EVAL SI5315 8KHZ-644.53MHZ
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5315-EVB

Main Purpose
Timing, Clock Multiplier
Embedded
No
Utilized Ic / Part
SI5315
Primary Attributes
2 Inputs, 2 Outputs
Secondary Attributes
CML, CMOS, LVDS, LVPECL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
S
Description
The Si5315 Evaluation Board User’s Guide provides for
a complete and simple evaluation of the functions,
features, and performance of the Si5315-EVB.
The
attenuating clock multiplier has a comprehensive
feature set, including any-rate frequency synthesis,
multiple clock inputs, multiple clock outputs, alarm and
status outputs, hitless switching between input clocks,
and programmable output clock signal format (LVPECL,
LVDS, CML, CMOS). For more details, consult the
Silicon
www.silabs.com/timing.
TheSi5315-EVB has two differential clock input and
Features
The Si5315-EVB includes the following:
Function Block Diagram
Rev. 0.2 6/09
DUT PWR
DUT PWR
1.8V to 3.3V
1.8V to 3.3V
I
CD with the Si5315 documentation and the Si5315-
EVB User’s Guide
5315-EVB U
Si5315
+3.3V
+3.3V
Labs
Synchronous
timing
+3.3V
+3.3V
Vreg
Vreg
USB
USB
products
SER
Ethernet/Telecom
LED power
LED power
To DUT
To DUT
Input
Input
SMAs
SMAs
Copyright © 2009 by Silicon Laboratories
S
website
G
UIDE
Jumper
Jumper
Headers
Headers
jitter
at:
Terminate
Terminate
Control signals
Control signals
output ports that are AC terminated to 50 ohms and
then AC coupled to the Si5315. The XA-XB reference is
usually a 40 MHz crystal; however, there are provisions
for an external XA-XB reference clock (either differential
or single ended).
The evaluation board (EVB) can be powered using two
different approaches: external power supplies or by
USB. Jumper plugs are provided to select between
these two options. Jumper plugs are used to strap the
device pins for the various pin value options. Status
outputs are available on a ribbon connector header.
SMA connectors are used for the clock input, output,
and XA-XB reference signals.
Evaluation board
Ext RefClk
Ext RefClk
Si5315
Si5315
Si 5315-EVB
CKOUT1
CKOUT1
CKOUT2
CKOUT2
status signals
status signals
LEDs
LEDs
Output
Output
SMAs
SMAs
Si5315-EVB

Related parts for SI5315-EVB

SI5315-EVB Summary of contents

Page 1

... LVDS, CML, CMOS). For more details, consult the Silicon Labs timing products www.silabs.com/timing. TheSi5315-EVB has two differential clock input and Features The Si5315-EVB includes the following: CD with the Si5315 documentation and the Si5315-  EVB User’s Guide Function Block Diagram ...

Page 2

... Si5315-EVB 1. Introduction The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates ...

Page 3

... XA-XB pins. To that end, the EVB is configured with a 40 MHz fundamental mode crystal connected between pins 6 and 7 of the Si5315. However, the Si5315-EVB is capable of using an external XA-XB reference oscillator, either differential or single ended. J1 and J2 are the SMA connectors with AC termination. AC coupling is also provided that needs to be installed at C6 and C8 ...

Page 4

... Si5315-EVB 2.4. Pin Configuration J12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the pins of the Si5315. Each pin can be strapped to be either achieved by installing a jumper plug between the appropriate middle row pin and its VDD row pin achieved by installing a jumper plug between the appropriate middle row pin and its GND row pin ...

Page 5

... Figure 2. Connectors, Headers, and Jumper Locations Table 2. LED Descriptions Label Significance CS_CA ON = clock input 2 selected, else clock 1 LOS2 valid clock input 2 LOS1 valid clock input 1 LOL ON = Si5315 is not locked DUT_PWR ON = Si5315 power is present 3. 3.3V power is present Preliminary Rev. 0.2 Si5315-EVB R8 R8 U1, U1, Si5315 Si5315 J15 J15 5 ...

Page 6

... Si5315-EVB *Note: Unused header pin locations should be left open. Table 4. Status Indication Header, J13 6 Table 3. Configuration Header, J12 J12 Pin J12.1 Not used* J12.2 SFOUT0 J12.3 SFOUT1 J12.4 FRQTBL J12.5 FRQSEL0 J12.6 FRQSEL1 J12.7 FRQSEL2 J12.8 FRQSEL3 J12.9 BWSEL0 J12.10 BSWEL1 J12 ...

Page 7

... Schematics VDD3 32 VDD2 10 VDD1 5 Rate0 11 Rate1 Preliminary Rev. 0.2 Si5315-EVB GND5 37 GND4 19 GND3 20 GND2 31 GND1 8 7 ...

Page 8

... Si5315-EVB PAD Preliminary Rev. 0 ...

Page 9

... L1, Q1,Q2,Q3,Q4, R2,R8,R12,R16 24 6 R3,R4,R5,R7,R9,R11 26 1 R14 27 2 R15,R20 28 2 R17,R18 29 1 R19 Table 5. Si5315-EVB Bill of Materials Part 10NF 100N 1UF 220UF 33UF Yel Panasonic Red Grn Panasonic SMA_EDGE 14x3_M_HDR_THRU 10_M_Header Phoenix_3_screw Jmpr_2pin Jmpr_3pin USB Jmpr_1pin Ferrite BSS138 0 ohm 49.9 10 10k ...

Page 10

... Si5315-EVB Item Qty Reference C6, R6,R10,R13 10 Table 5. Si5315-EVB Bill of Materials Part FAN1540B 40 MHz Not Populated 10NF Jmpr_2pin 100 0 ohm Preliminary Rev. 0.2 Mfr Manufacturer Part No. Fairchild FAN1540BPMX Abracon ABM8-40.000 MHz-BZT Venkel C0603X7R160-103KNE Venkel CR0603-16W-1000FT Venkel CR0603-16W-000T ...

Page 11

... Layout Figure 5. Silkscreen Top Preliminary Rev. 0.2 Si5315-EVB 11 ...

Page 12

... Si5315-EVB 12 Figure 6. Layer 1 Preliminary Rev. 0.2 ...

Page 13

... Figure 7. Layer 2—Ground Plane Preliminary Rev. 0.2 Si5315-EVB 13 ...

Page 14

... Si5315-EVB 14 Figure 8. Layer 3 Preliminary Rev. 0.2 ...

Page 15

... Figure 9. Layer 4 Preliminary Rev. 0.2 Si5315-EVB 15 ...

Page 16

... Si5315-EVB 16 Figure 10. Layer 5, FILT_DUT_PWR Preliminary Rev. 0.2 ...

Page 17

... Figure 11. Layer 6, Bottom Preliminary Rev. 0.2 Si5315-EVB 17 ...

Page 18

... Si5315-EVB 18 Figure 12. Bottom Silkscreen Preliminary Rev. 0.2 ...

Page 19

... Jumper installed on J15 (labeled ONE POWER) J12 Pin Jumper J12.1 Not used — J12.2 SFOUT0 H J12.3 SFOUT1 M J12.4 FRQTBL H J12.5 FRQSEL0 L J12.6 FRQSEL1 H J12.7 FRQSEL2 M J12.8 FRQSEL3 L J12.9 BWSEL0 H J12.10 BSWEL1 H J12.11 DBL2_BY L J12.12 AUTOSEL H J12.13 XTAL/CLOCK L J12.14 Not used — Preliminary Rev. 0.2 Si5315-EVB 19 ...

Page 20

... Si5315-EVB N : OTES 20 Preliminary Rev. 0.2 ...

Page 21

... D C OCUMENT HANGE LIST Revision 0.1 to Revision 0.2 Removed Si5315-EVB from Appendix of Si5315-  EVB, Si5316-EVB, Si5319-EVB, Si532/23-EVB, Si5325/26-EVB with Si5315-EVB Appendix B User’s Guide Revised Revision 0 stand-alone Si5315-EVB  User’s Guide Preliminary Rev. 0.2 Si5315-EVB 21 ...

Page 22

... Si5315-EVB C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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