EVK-DS40MB200 National Semiconductor, EVK-DS40MB200 Datasheet - Page 6

• Manufacturer Part Number: EVK-DS40MB200
• Description: BOARD EVALUATION DS40MB200
• Manufacturer: National Semiconductor

Specifications of EVK-DS40MB200

• Main Purpose: Interface, 2:1 Multiplexer
• Utilized Ic / Part: DS40MB200
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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Functional Description
The DS40MB200 is a signal conditioning 2:1 multiplexer and
a 1:2 buffer designed to support port redundancy up to 4.0
Gbps. The high speed inputs are self-biased to about 1.3V
and are designed for AC coupling, see Figure 6 for details..
The inputs are compatible to most AC coupling differential
signals such as LVDS, LVPECL and CML. The DS40MB200
is not designed to operate with data rates below 1000 Mbps
or with a DC bias applied to the CML inputs or outputs. Most
high speed links are encoded for DC balance and have been
defined to include AC coupling capacitors allowing the
DS40MB200 to be directly inserted into the datapath without
any limitation. The ideal AC coupling capacitor value is often
based on the lowest frequency component embedded within
the serial link. A typical AC coupling capacitor value ranges
between 100 and 1000nF, some specifications with scram-
bled data may require a larger capacitor for optimal perfor-
mance. To reduce unwanted parasitics around and within the
AC coupling capacitor, a body size of 0402 is recommended.
PreL_[1:0]
(default)
0 0
0 1
1 0
1 1
MUX_S0
0
1 (default)
MUX_S1
0
1 (default)
LB0A
0
1 (default)
LB0B
0
1 (default)
LB1A
0
1 (default)
LB1B
0
1 (default)
Pre-Emphasis Level in
(VODB)
mV
1200
1200
1200
1200
TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS
TABLE 2. LOGIC TABLE FOR LOOPBACK Controls
TABLE 3. LINE-SIDE PRE-EMPHASIS CONTROLS
PP
Mux Function
MUX_0 select switch_B input, SIB_0±.
MUX_0 select switch_A input, SIA_0±.
Mux Function
MUX_1 select switch_B input, SIB_1±.
MUX_1 select switch_A input, SIA_0±.
Loopback Function
Enable loopback from SIA_0± to SOA_0±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIB_0± to SOB_0±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIA_1± to SOA_1±.
Normal mode. Loopback disabled.
Loopback Function
Enable loopback from SIB_1± to SOB_1±.
Normal mode. Loopback disabled.
De-Emphasis Level
(VODPE)
in mV
1200
850
600
426
6
PP
Figure 5 shows the AC coupling capacitor placement in an AC
test circuit
Each input stage has a fixed equalizer that provides equal-
ization to compensate about 5 dB of transmission loss from a
short backplane trace (about 10 inches backplane). The out-
put driver has Pre-emphasis (driver-side equalization) to
compensate the transmission loss of the backplane that it is
driving. The driver conditions the output signal such that the
lower frequency and higher frequency pulses reach approxi-
mately the same amplitude at the end of the backplane, and
minimize the deterministic jitter caused by the amplitude dis-
parity. The DS40MB200 provides four steps of user-se-
lectable Pre-emphasis ranging from 0, -3, -6 and –9 dB to
handle different lengths of backplane. Figure 1 shows a driver
Pre-emphasis waveform. The Pre-emphasis duration is
200ps nominal, corresponds to 0.8 bit-width at 4.0 Gbps. The
Pre-emphasis levels of switch-side and line-side can be indi-
vidually programmed.
Pre-Emphasis in dB
(VODPE/VODB)
−3
−6
−9
0
10 inches
20 inches
30 inches
40 inches
Typical FR4 board
trace