LMK04000BEVALXO National Semiconductor, LMK04000BEVALXO Datasheet - Page 50

• Manufacturer Part Number: LMK04000BEVALXO
• Description: BOARD EVAL PREC CLOCK PLL XO
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMK04000BEVALXO

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK04000
• Primary Attributes: 122.88 MHz Crystal
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Appendix H: LMK04000
The block diagram in Figure 27 illustrates the functional architecture of the LMK040xxB clock
conditioner. It features a cascaded, dual PLL arrangement, available internal loop filter
components for PLL2, internal VCO with PLL2 for frequency synthesis, and clock distribution
section with individual clock output dividers and delay adjustment blocks. The dual reference
clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded
PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that
contains excessive phase noise. This requires the user to select an external oscillator (VCXO or
crystal) that provides the desired phase noise performance at the clock output. This external
oscillator becomes the reference clock for PLL2 and along with the phase noise characteristics of
PLL2 and the internal VCO, determines the final phase noise performance at FOUT and the
output of the clock distribution section.
Figure 27 - Functional Block Diagram of the LMK040xxB Dual PLL Precision Clock Conditioner with
CLKin0
CLKin1
DATA
CLK
LE
Interface
uWire
L M K 0 4 0 X X - R E V 3
R
1
PLL1
vcxo
N
1
E V A L U A T I O N
External VCXO module.
R
2
PLL2
50
N
B O A R D
2
CHAN
CHAN
DIV
DIV
VCO
DIV
O P E R A T I N G
LVPECL, LVDS,
5 Output Clock
VCO
Channels
LVCMOS
I N S T R U C T I O N S
CLKout_0
CLKout_4
F
OUT