SI5017-EVB Silicon Laboratories Inc, SI5017-EVB Datasheet - Page 2

• Manufacturer Part Number: SI5017-EVB
• Description: BOARD EVALUATION FOR SI5017
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5017-EVB

• Main Purpose: Timing, Clock and Data Recovery (CDR)
• Utilized Ic / Part: SI5017
• For Use With/related Products: Si5017
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1125

Si5017-EVB
Functional Description
The evaluation board simplifies characterization of the
Si5017 Clock and Data Recovery (CDR) device by
providing access to all of the Si5017 I/Os. Device
performance can be evaluated by following the “Test
Configuration” section. Specific performance metrics
include input sensitivity, jitter tolerance, jitter generation,
and jitter transfer.
Power Supply
The evaluation board requires one 3.3 V supply. Supply
filtering is placed on the board to filter typical system
noise components; however, initial performance testing
should use a linear supply capable of supplying the
nominal voltage ±5% dc.
CAUTION: The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 3.3 V relative to chassis
GND.
Device Powerdown
The CDR can be powered down via the RESET/CAL
signal. When asserted, the evaluation board draws
minimal current. RESET/CAL is controlled via one
jumper located in the lower left-hand corner of the
evaluation board. RESET/CAL is wired to the signal
post adjacent to the VDD post. For a valid reset to occur
when using external reference clock mode, a proper
external reference clock frequency must be applied as
specified in Table 1. CLKOUT, DATAOUT, DATAIN
CLKOUT, DATAOUT, and DATAIN (all high-speed I/Os)
are wired to the board perimeter on 30 mil (0.030 inch)
50 Ω microstrip lines to the end-launch SMA jacks as
labeled on the PCB. These I/Os are ac coupled to
simplify direct connection to a wide array of standard
test hardware. Because each of these signals are
differential, both the positive (+) and negative (–)
terminals must be terminated to 50 Ω. Terminating only
one side will adversely degrade the performance of the
CDR. The inputs are terminated on the die with 50 Ω
resistors.
Note: The 50 Ω termination is for each terminal/side of a dif-
REFCLK
REFCLK is optional for clock and data recovery within
the Si5017 device. If REFCLK is not used, jumper both
JP15 and JP16. These jumpers pull the REFCLK+ input
to VDD and REFCLK– input to GND, which configures
the device to operate without an external reference.
2
ferential signal, thus the differential termination is actu-
ally 50 Ω + 50 Ω = 100 Ω.
Rev. 1.0
When applied, REFCLK is used to center the frequency
of the DSPLL™ so the device can lock to the data.
Ideally, the REFCLK frequency should be 1/128th,
1/32nd, or 1/16th the VCO frequency and must have a
frequency accuracy of ±100 ppm. Internally, the CDR
automatically recognizes the REFCLK frequency within
one of these three frequency ranges. Typical REFCLK
frequencies are given in Table 1. REFCLK is ac coupled
to the SMA jacks located on the top side of the
evaluation board.
Loss-of-Lock (LOL)
Loss-of-lock (LOL) is an indicator of the relative
frequency between the data and the REFCLK. LOL
asserts when the frequency difference is greater than
±600 ppm.
prematurely, there is hysterisis in returning from the out-
of-lock condition. LOL will be de-asserted when the
frequency difference is less than ±300 ppm.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Loss-of-Signal Alarm Threshold Control
The loss-of-signal alarm (LOS) is used to signal low
incoming data amplitude levels. The programmable
threshold control is set by applying a dc voltage level
from a low noise voltage source to the LOS_LVL pin.
The LOS_LVL is controllable through the BNC jack J10.
The mapping of the LOS_LVL voltage to input signal
alarm threshold level is shown in Figure 1. The LOS
Threshold to LOS Level is mapped as follows:
If this function is not used, install jumper to JP1 header.
Table 1. Typical REFCLK Frequencies
SONET/SDH
155.52 MHz
19.44 MHz
77.76 MHz
To
V
LOS
prevent
SONET/SDH
=
166.63 MHz
15/14 FEC
20.83 MHz
83.31 MHz
V
---------------------------------------
LOS_LVL
with
LOL
25
–
1.5
from
REFCLK
Ratio of
VCO to
128
32
16
de-asserting