SI5310-EVB Silicon Laboratories Inc, SI5310-EVB Datasheet - Page 3

• Manufacturer Part Number: SI5310-EVB
• Description: BOARD EVALUATION FOR SI5310
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5310-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5310
• Processor To Be Evaluated: Si5310
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1140

Loss-of-Lock (LOL)
LOL is an indicator of the relative frequency between
the REFCLK input, which is nominally a multiple of
CLKIN, and an internally generated multiple of CLKIN.
LOL will assert when the frequency difference is greater
than ±600 PPM. In order to prevent LOL from de-
asserting prematurely, there is hysterisis in returning
from the out of lock condition. LOL will be de-asserted
(indicating a lock condition) when the frequency
difference is less than ±300 PPM.
LOL is wired to a test point which is located on the
Note:
(MULTOUT = 600–668 MHz)
(MULTOUT = 150–167 MHz)
Figure 1. MULTSEL Jumper Configurations
60 0 – 6 68 M Hz
High Ra nge
MULTSEL
1. The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple.
MULTSEL
0
1
MU L TSEL
PWR D N /
C AL
Table 1. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
1 5 0 – 16 7 MHz
Low Ra nge
MULTSEL
150.000–167.000
300.000–334.000
600.000–668.000
150.000–167.000
37.500–41.750
75.000–83.500
18.750–20.875
37.500–41.750
75.000–83.500
CLKIN Range
9.375–10.438
(MHz)
MU L TSEL
PWR D N /
C AL
Preliminary Rev. 0.71
n = –5, –4, –3, –2, or –1
n = –6, –5, –4, –3, or –2
REFCLK = 2
n = –4, –3, –2, –1, or 0
n = –4, –3, –2, –1, or 0
n = –3, –2, –1, 0, or 1
n = –3, –2, –1, 0, or 1
n = –2, –1, 0, 1, or 2
n = –2, –1, 0, 1, or 2
n = –1, 0, 1, 2, or 3
n = 0, 1, 2, 3, or 4
upper right-hand side of the evaluation board.
Test Configuration
The characterization of clock sources typically involves
measuring the output jitter or phase noise of the source.
The overall output jitter is a function of the input jitter
(jitter transfer) and the jitter generated (output jitter) by
the internal PLL.
Jitter can
techniques and hardware. An oscilloscope, a spectrum
analyzer, and a phase-noise analyzer are three such
instruments capable of measuring output jitter. A
spectrum analyzer is the best choice for measuring jitter
transfer.
Output Jitter
Output jitter is a measure of the output clock short-term
stability. In Figure 2, either position A or B can be used
when measuring this parameter.
Oscilloscope
An oscilloscope can measure jitter from the clock edges
within the trigger-to-capture bandwidth. Typically the
jitter measured is expressed in picoseconds (peak-to-
peak and RMS) relative to the average edge position. A
histogram can be used to capture the jitter distribution.
(see Note 2)
±100 ppm
n
x CLKIN
be
measured using several different
See Note 1
See Note 1
CLKOUT
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
1xCLKIN
Si5310-EVB
MULTOUT
16xCLKIN
16xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN
8xCLKIN
4xCLKIN
2xCLKIN
1xCLKIN
3