CLINK3V28BT-85 National Semiconductor, CLINK3V28BT-85 Datasheet - Page 11

• Manufacturer Part Number: CLINK3V28BT-85
• Description: KIT EVAL 28BIT DS90CR287/288A
• Manufacturer: National Semiconductor

Specifications of CLINK3V28BT-85

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS90CR287, DS90CR288A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 7) + ISI (Inter-symbol interference)(Note 8)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 7: Cycle-to-cycle jitter is less than 150ps at 85MHz.
Note 8: ISI is dependent on interconnect length; may be zero
DS90CR287 MTD56 (TSSOP) Package Pin Description — Channel Link
Transmitter
DS90CR288A MTD56 (TSSOP) Package Pin Description — Channel Link
Receiver
CC
CC
Pin Name
Pin Name
CC
CC
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No.
No.
28
28
4
4
1
1
1
1
4
5
1
2
1
3
4
4
1
1
1
1
4
TTL level input.
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See
Applications Information section.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down. See Applications Information section.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
(Continued)
FIGURE 16. Receiver LVDS Input Skew Margin
11
Description
Description
10108720
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