CLINK3V48BT-112 National Semiconductor, CLINK3V48BT-112 Datasheet - Page 11

• Manufacturer Part Number: CLINK3V48BT-112
• Description: KIT EVAL 48BIT DS90CR481/2/3/4
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-112

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS90CR481, DS90CR482, and DS90CR483
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
See Applications Information section for more details.
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
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j
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Cable Skew — typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
d= Tppos — Transmitter output pulse position (min and max)
f= Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate)
m= extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKM) for Chipset without DESKEW
FIGURE 14. Receiver Skew Margin (RSKMD) for Chipset with DESKEW
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