MAX11046EVKIT+ Maxim Integrated Products, MAX11046EVKIT+ Datasheet - Page 10

• Manufacturer Part Number: MAX11046EVKIT+
• Description: KIT EVALUATION FOR MAX11046
• Manufacturer: Maxim Integrated Products

Specifications of MAX11046EVKIT+

• Silicon Manufacturer: Maxim
• Silicon Core Number: MAX11046
• Kit Application Type: Data Converter
• Application Sub Type: ADC
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
10
22, 28, 35, 43,
23, 27, 33, 38,
(TQFN-EP)
MAX11044
7, 21, 50
8, 20, 51
______________________________________________________________________________________
44, 48
10
11
12
13
14
15
16
17
18
19
49
1
2
3
4
5
6
9
22, 28, 35, 43,
23, 27, 33, 38,
MAX11045
(TQFN-EP)
7, 21, 50
8, 20, 51
44, 48
PIN
10
11
12
13
14
15
16
17
18
19
49
1
2
3
4
5
6
9
22, 28, 35, 43,
23, 27, 33, 38,
(TQFN-EP)
MAX11046
7, 21, 50
8, 20, 51
44, 48
10
11
12
13
14
15
16
17
18
19
49
1
2
3
4
5
6
9
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
CONVST
AGNDS
NAME
DGND
DVDD
SHDN
DB13
DB12
DB11
DB10
EOC
RDC
DB9
DB8
DB7
DB6
DB5
DB4
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor
at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital Output Bit 3/
Configuration Register Input Bit 3
16-Bit Parallel Data Bus Digital Output Bit 2/
Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
C onver t S tar t Inp ut. Ri si ng ed g e of C ON V S T end s
sam p l e and star ts a conver si on on the cap tur ed sam p l e.
The AD C i s i n acq ui si ti on m od e w hen C ON V S T i s l ow
and C ON V S T m od e = 0.
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
Refer ence Buffer D ecoup l i ng . C onnect al l RD C outp uts
tog ether . Byp ass to AG N D w i th at l east an 80µF total
cap aci tance. S ee the Layout, Gr ound i ng , and Byp assi ng
secti on.
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
FUNCTION
Pin Description