AD9262-5EBZ Analog Devices Inc, AD9262-5EBZ Datasheet - Page 3

• Manufacturer Part Number: AD9262-5EBZ
• Description: BOARD EVALUATION 5MHZ AD9262
• Manufacturer: Analog Devices Inc

Specifications of AD9262-5EBZ

• Design Resources: Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 160M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 Vpp
• Power (typ) @ Conditions: 547mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9262
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9262
• Kit Contents: Software, Evaluation Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Evaluation Board User Guide
PRODUCT FEATURES
Table 1.
AD9262
SNR: 82.5 dB (84.5 dBFS) to
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 675 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
Output data rate: 30 MSPS to
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, gray code, or twos
Serial control interface (SPI)
ADR130B
Initial accuracy
Maximum temperature coefficient
C
Output current: +4 mA/−2 mA
Low operating current: 80 μA
Output noise: 6 μV p-p @ 1.0 V
Input range: 2.0 V to 18 V
Temperature range: −40°C to
Tiny Pb-free TSOT package
LOAD
10 MHz input
2.5 MHz/5 MHz/10 MHz real
5 MHz/10 MHz/20 MHz complex
160 MSPS
complement data format
A grade: ±0.70% (maximum)
B grade: ±0.35% (maximum)
A grade: 50 ppm/°C
B grade: 25 ppm/°C
(typical)
output
+125°C
: 50 nF to 10 μF
ADL5382
I/Q demodulator
Operating RF frequency: 700 MHz to
IIP3 + 30 dBm
IIP2 + 60 dBm
Input P1dB + 13dBm
NF 14 dB @ 900 MHz
Voltage conversion gain: 5 dB
Quadrature demodulation accuracy
LO input: −10 dBm to +5 dBm
Demodulation bandwidth: ~500 MHz
I/Q drive 2 V
Programmable power consumption
ADP3339
High accuracy over line and load: ±0.9% @
Ultralow dropout voltage: 230 mV (typical)
Requires only C
anyCAP® regulators: stable with any type
Current and thermal limiting
Low noise
2.8. V to 6 V supply range
−40°C to +85°C ambient temperature
SOT-223 package
2700 MHz
Phase accuracy <0.5°
Amplitude balance <0.25 dB
25°C, ±1.5% over temperature
@ 1.5 A
of capacitor (including MLCC)
range
PEAK
O
into 200 Ω
= 1.0 μF for stability
Rev. 0 | Page 3 of 24
AD9516-0
Low phase noise, phase-locked loop
Three pairs of 1.6 GHz LVPECL outputs
Two pairs of 800 MHz LVDS clock outputs
Eight 250 MHz CMOS outputs (two per LVDS output)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
Serial control port
64-lead LFCSP
ADA4937
Extremely low harmonic distortion
Low input voltage noise: 2.2 nV/√Hz
High speed
1 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended–to-
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
Pb-free, 3 mm × 3 mm 16-lead LFCSP
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz (optional)
One differential or two single-ended reference
Reference monitoring capability
Auto and manual reference switchover/holdover
Autorecover from holdover
Accepts references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
Each pair shares one to 32 dividers with coarse
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs: <10 ps
Each pair shares two cascaded one-to-32 dividers
Additive output jitter: 275 fs rms
Fine delay adjust (ΔT) on each LVDS output
−112 dBc HD2 @ 10 MHz
−79 dBc HD2 @ 70 MHz
−70 dBc HD2 @ 10 MHz
−102 dBc HD3 @ 10 MHz
−91 dBc HD3 @ 70 MHz
−84 dBc HD3 @ 100 MHz
−3 dB bandwidth of 1.0 GHz, G = 1
Slew rate: 6000 V/μs, 25% to 75%
dB gain flatness to 200 MHz
Fast overdrive recovery of 1 ns
differential operation
inputs
modes
phase delay
with coarse phase delay
UG-051