ADC14DS080LFEB/NOPB National Semiconductor, ADC14DS080LFEB/NOPB Datasheet
ADC14DS080LFEB/NOPB
Specifications of ADC14DS080LFEB/NOPB
Related parts for ADC14DS080LFEB/NOPB
ADC14DS080LFEB/NOPB Summary of contents
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... ADC14DS80 functionality. The ADC14DS080 is available in a 60-lead LLP package and operates over the industrial tem- perature range of −40°C to +85°C. Connection Diagram © 2007 National Semiconductor Corporation Features ■ Clock Duty Cycle Stabilizer ■ ...
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Block Diagram Ordering Information Industrial (−40°C www.national.com ≤ ≤ T +85°C) A ADC14DS080CISQ ADC14DS080LFEB Evaluation Board for Input Frequency < 70 MHz 2 30035802 Package 60 Pin LLP ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I CMO 9 V ...
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Pin No. Symbol 57 PD_A 20 PD_B 27 TEST 47 WAM 48 DLC 45 OUTCLK+ 44 OUTCLK- 43 FRAME+ 42 FRAME- www.national.com Equivalent Circuit This is a two-state input controlling Power Down Power Down is enabled ...
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Pin No. Symbol Equivalent Circuit 38 SD1_A+ 37 SD1_A- 34 SD1_B+ 33 SD1_B- 36 SD0_A+ 35 SD0_A- 32 SD0_B+ 31 SD0_B- 56 SPI_EN 55 SCSb 52 SCLK 54 SDI Description Serial Data Output 1 for Channel A. This is a ...
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Pin No. Symbol 53 SDO 46 ORA 30 ORB 24 DLL_Lock ANALOG POWER 8, 16, 17, 58 12, 15, AGND Exposed Pad DIGITAL POWER 26, 40 25, 39, 51 DRGND www.national.com Equivalent ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Pin (Not to exceed 4.2V) Input Current at Any Pin other than Supply Pins (Note 4) Package Input Current (Note 4) ...
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Symbol Parameter Internal Reference Accuracy EXT External Reference Voltage V REF Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V MHz pF/pin, ...
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Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V MHz pF/pin. Typical values are for T CLK CM CMO L ...
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LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V MHz pF/pin. Typical values are for T CLK CM CMO L amplitude. Boldface limits ...
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Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Note 4: When the input voltage at any pin exceeds the power supplies (that is, V ±50 mA maximum package input ...
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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Timing Diagrams FIGURE 2. Serial Output Data Format in Single-Lane Mode FIGURE 1. Serial Output Data Timing 13 30035814 30035817 www.national.com ...
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FIGURE 3. Serial Output Data Format in Dual-Lane Mode www.national.com 14 30035818 ...
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Transfer Characteristic FIGURE 4. Transfer Characteristic 15 30035810 www.national.com ...
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Typical Performance Characteristics DNL, INL specifications apply: AGND = DRGND = 0V, V disabled 25°C. CM CMO A DNL www.national.com Unless otherwise specified, the following = V = +3.0V, Internal V = +1.2V, f ...
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Typical Performance Characteristics AGND = DRGND = 0V +3.0V, Internal MHz 25° SNR, SINAD, SFDR vs. V SNR, SINAD, SFDR vs. Clock Duty Cycle SNR, SINAD, ...
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Spectral Response @ 10 MHz Input Spectral Response @ 170 MHz Input www.national.com Spectral Response @ 70 MHz Input 30035868 IMD MHz 30035870 18 30035869 MHz IN 30035871 ...
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Functional Description Operating on a single +3.3V supply, the ADC14DS080 digi- tizes two differential analog input signals to 14 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user ...
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− REF CM V − REF − REF CM V ...
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Loading any of these pins, other than V may result in performance degradation. CMO The nominal voltages for the reference bypass pins are as follows 1.5 V CMO ...
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SCSb, SDI, SCLK These pins are part of the SPI interface. See Section 5.0 for more information. 4.0 DIGITAL OUTPUTS Digital outputs consist of six LVDS signal pairs (SD0_A, SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS logic outputs ORA, ...
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DCS, PD_A, PD_B, DLC, WAM, TEST) have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are enabled. Each serial interface access cycle is exactly 16 bits long. Fig- ure 10 shows ...
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Device Control Register, Address DLC DCS OF WAM PD_A PD_B Reset State : 08h Bits (7:6) Operational Mode 0 0 Normal Operation Test Output mode. A fixed test pattern (10100110001110 ...
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Reset State : 00h Bits (7:6) Reserved. Must be set to '0'. Bits (5:0) User Test Pattern. Most-significant 6 bits of the 14-bit pattern that will be sourced out of the data outputs in Test Output Mode. User Test Pattern ...
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Physical Dimensions TOP View...............................SIDE View...............................BOTTOM View www.national.com inches (millimeters) unless otherwise noted 60-Lead LLP Package Ordering Numbers: ADC14DS080CISQ NS Package Number SQA60A 26 ...
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Notes 27 www.national.com ...
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