HI5767EVAL2 Intersil, HI5767EVAL2 Datasheet

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HI5767EVAL2

Manufacturer Part Number
HI5767EVAL2
Description
EVALUATION PLATFORM HI5767
Manufacturer
Intersil
Datasheets

Specifications of HI5767EVAL2

Number Of Adc's
1
Number Of Bits
10
Sampling Rate (per Second)
60M
Data Interface
Parallel
Inputs Per Adc
1 Differential
Input Range
1 Vpp
Power (typ) @ Conditions
310mW @ 60MSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
HI5767
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Description
The HI5767EVAL2 evaluation board allows the circuit
designer to evaluate the performance of the Intersil HI5767
monolithic 10-bit 20/40/60MSPS analog-to-digital converter
(ADC). As shown in the Evaluation Board Functional Block
Diagram, the evaluation board includes sample clock
generation circuitry, a single-ended to differential analog
input RF transformer configuration, an on board external
variable reference voltage generator and a digital data
output header/connector. The digital data outputs are
conveniently provided for easy interfacing to a ribbon
connector or logic probes. In addition, the evaluation board
includes some prototyping area for the addition of user
designed custom interfaces or circuits.
The sample clock generator circuit accepts the external
sampling signal through an SMA type RF connector, J2.
This input is AC-coupled and terminated in 50 allowing for
connection to most laboratory signal generators. In
addition, the duty cycle of the clock driving the A/D
Evaluation Board Functional Block Diagram
DGND
ANALOG
SAMPLE
CLOCK
INPUT
INPUT
AGND
REFERENCE
BANDGAP
VOLTAGE
J2
1.2V
J1
+5V
D
50
+5V
A
+5V
TM
3-1
D
-5V
A
BIAS
TEE
1-888-INTERSIL or 321-724-7143
TRANSFORMER
Application Note
GAIN
VAR
HI5767EVAL2 Evaluation Board User’s Manual
RF
+2.5V
|
Intersil and Design is a trademark of Intersil Corporation.
V
V
V
V
converter is adjustable by way of a potentiometer. This
allows the effects of sample clock duty cycle on the HI5767
to be observed.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input RF transformer. This input is
AC-coupled and terminated in 50
to most laboratory signal generators.
The converters’ digital data outputs along with two phases of
the sample clock (CLK and CLK) are provided at the output
header/connector. With this output configuration the digital
data output transitions seen at the I/O header/connector are
essentially time aligned with the rising edge of the sampling
clock (CLK) or the falling edge of the out of phase sampling
clock (CLK).
Refer to the component layout and the evaluation board
electrical schematic for the following discussions.
REFIN
REFOUT
IN
IN
+
-
HI5767
CLK
D
0
January 1999
-D
9
10
|
Copyright
allowing for connection
©
Intersil Corporation 2000
CLK
CLOCK
OUT
CLK
DIGITAL
DATA
OUT
(D0 - D9)
AN9762

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HI5767EVAL2 Summary of contents

Page 1

... TM Application Note Description The HI5767EVAL2 evaluation board allows the circuit designer to evaluate the performance of the Intersil HI5767 monolithic 10-bit 20/40/60MSPS analog-to-digital converter (ADC). As shown in the Evaluation Board Functional Block Diagram, the evaluation board includes sample clock generation circuitry, a single-ended to differential analog ...

Page 2

... The external variable reference voltage circuitry is implemented using the Intersil ICL8069 low voltage, 1.2V, bandgap reference (D1) sourcing a non-inverting variable gain operational amplifier circuit based on the Intersil HA5127 ultra-low noise precision operational amplifier (U1). Potentiometer VR1 is used to adjust the output voltage level of this external voltage reference ...

Page 3

... This is the type of single-ended to differential conversion circuitry that is provided on the HI5767EVAL2 evaluation board (refer to the HI5767EVAL2 evaluation board parts layout and the electrical schematics). The HI5767EVAL2 evaluation board provides the single- ended to differential analog front-end for converting the typical laboratory signal generators 50 single-ended output to a differential input signal for the converters differential-in- differential-out sample-and-hold front end ...

Page 4

... Evaluating the part with a reconstruction DAC is only suggested when doing bandwidth or video testing. HP8662A COMPARATOR FIGURE 3. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM HP8662A REF BANDPASS FILTER CLK HI5767 CLK DIGITAL DATA OUTPUT HI5767EVAL2 14 EVALUATION BOARD DAS9200 GPIB ...

Page 5

... Appendix A Board Layout FIGURE 4. HI5767EVAL2 EVALUATION BOARD PARTS LAYOUT (NEAR SIDE) FIGURE 5. HI5767EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE (LAYER 1) 3-5 Application Note 9762 ...

Page 6

... Appendix A Board Layout FIGURE 6. HI5767EVAL2 EVALUATION BOARD GROUND PLANE LAYER (LAYER 2) FIGURE 7. HI5767EVAL2 EVALUATION BOARD POWER PLANE LAYER (LAYER 3) 3-6 Application Note 9762 (Continued) ...

Page 7

... Appendix A Board Layout FIGURE 8. HI5767EVAL2 EVALUATION BOARD COMPONENT FAR SIDE (LAYER 4) FIGURE 9. HI5767EVAL2 EVALUATION BOARD PARTS LAYOUT (FAR SIDE) 3-7 Application Note 9762 (Continued) ...

Page 8

D2 + C32 C28 4.7 F 0 C24 4 C25 0.1 F 0.1 F EXT V REF + C26 C29 C27 ...

Page 9

Appendix B Schematic Diagrams C11 J1 0.1 F VIN R3 A/R SINGLE-ENDED TO DIFFERENTIAL (TRANSFORMER) ANALOG FRONT END 3-9 Application Note 9762 (Continued) ZIN:ZOUT C10 (1:4) 0 T4-1-KK81 C12 3 C31 4 0.1 F 0.1 ...

Page 10

Appendix B Schematic Diagrams + 4 4.99K 4 ICL8069CCBA C6 C2 0.1 F 0.1 F 3-10 Application Note 9762 (Continued ...

Page 11

Appendix B Schematic Diagrams C42 C38 J2 0.1 F 0.1 F CLK IN R12 56.2 +5V 1(CCW VR2 1.0K 3(CW) C40 C41 4.7 F 0.1 F R11 100 AGND TEST POINT TP1 TP3 E9 E10 FB5 +5V AIN ...

Page 12

Appendix B Schematic Diagrams D0 - D9, CLK4 (CLK) 3-12 Application Note 9762 (Continued) P1C C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 CLK4 ...

Page 13

... U2 1 Intersil HI5767 10-Bit 20/40/60MSPS A/D Converter with Internal Voltage Reference U1 1 Intersil HA9P5127-5 8.5MHz, Ultra-Low Noise Precision Operational Amplifier U3 1 Intersil CD74HC04M High Speed CMOS Logic Hex Inverter D1 1 Intersil ICL8069CCBA Low Voltage Bandgap Reference P1 6 64-Pin Eurocard RT Angle Receptacle ...

Page 14

Appendix D HI5767 Theory of Operation The HI5767 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 10 depicts the circuit for the front end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an ...

Page 15

HI5767 Functional Block Diagram S 3-15 Application Note 9762 BIAS STAGE 1 2-BIT 2-BIT FLASH DAC STAGE 8 2-BIT 2-BIT FLASH DAC STAGE 9 2-BIT FLASH ...

Page 16

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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