ADC12DL040EVAL National Semiconductor, ADC12DL040EVAL Datasheet
ADC12DL040EVAL
Specifications of ADC12DL040EVAL
Related parts for ADC12DL040EVAL
ADC12DL040EVAL Summary of contents
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... An evaluation board is available to ease the evalua- tion process. Connection Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation Features n Single +3.0V supply operation n Internal sample-and-hold n Internal reference n Outputs 2 ...
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... Ordering Information Industrial (−40˚C ≤ T ADC12DL040CIVS ADC12DL040EVAL Block Diagram www.national.com ≤ +85˚C) Package A 64 Pin TQFP Evaluation Board 2 20100202 ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I A− B− REF 21 DF/DCS ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol MULTIPLEX 24–29 DA0–DA11 34–39 43–47 DB1–DB11 52–57 42 DB0/ABb ANALOG POWER 9, 18 10, 17, AGND 20, 61, 64 DIGITAL POWER 33, ...
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... Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications – Voltage on Any Input or Output Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation 25˚C A ESD Susceptibility ...
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Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V +2.5V 0V, External V = +1.0V, f REF parallel output mode. Boldface limits apply for T Symbol Parameter ...
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DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V +2.5V 0V +1.0V, f REF CLK output mode. Boldface limits apply for T Symbol ...
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AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V +2.5V 0V, External V = +1.0V, f REF parallel output mode. Boldface limits apply for T Symbol Parameter ...
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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Timing Diagram www.national.com Output Timing 10 20100209 ...
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Transfer Characteristic FIGURE 1. Transfer Characteristic 11 20100210 www.national.com ...
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Typical Performance Characteristics DNL, INL specifications apply for AGND = DGND = DR GND = 0V, V MHz ns pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits ...
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Typical Performance Characteristics DNL, INL specifications apply for AGND = DGND = DR GND = 0V, V MHz ns pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits ...
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Typical Performance Characteristics for AGND = DGND = DR GND = 0V ns pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for all other ...
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Typical Performance Characteristics for AGND = DGND = DR GND = 0V ns pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for all other ...
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Typical Performance Characteristics for AGND = DGND = DR GND = 0V ns pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for all other ...
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Typical Performance Characteristics for AGND = DGND = DR GND = 0V ns pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for all other ...
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Functional Description Operating on a single +3.0V supply, the ADC12DL040 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of ...
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Applications Information Where dev is the angular difference in degrees between the two signals having a 180˚ relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100Ω. 20100212 FIGURE 3. ...
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Applications Information 2.0 DIGITAL INPUTS Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, PD, DF/DCS, and MULTIPLEX. 2.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock ...
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Applications Information data in the ASIC thus avoiding the use of the CLK signal altogether. However, since the ABb signal edges are pro- vided in-phase with the data transitions, generally the ASIC circuitry would have to delay the ABb signal ...
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Applications Information FIGURE 5. Application Circuit using Transformer or Differential Op-Amp Drive Circuit, Multiplex mode www.national.com (Continued) FIGURE 6. Differential Drive Circuit of Figure 4 22 20100266 20100214 ...
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Applications Information 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor within a centimeter of each power pin. Leadless chip capacitors are preferred because they ...
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Applications Information Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their ...
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Applications Information FIGURE 8. Isolating the ADC Clock from other Circuitry with a Clock Tree 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than ...
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