ADC08D1000DEV/NOPB National Semiconductor, ADC08D1000DEV/NOPB Datasheet
ADC08D1000DEV/NOPB
Specifications of ADC08D1000DEV/NOPB
Related parts for ADC08D1000DEV/NOPB
ADC08D1000DEV/NOPB Summary of contents
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... Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Indus- ≤ ≤ trial (-40°C T +85°C) temperature range. A Block Diagram © 2009 National Semiconductor Corporation ADC08D1000 Features ■ Internal Sample-and-Hold ■ Single +1.9V ±0.1V Operation ■ Choice of SDR or DDR output clocking ■ ...
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Ordering Information Industrial Temperature Range (-40°C < T ADC08D1000CIYB ADC08D1000DEV Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com < +85°C) A 128-Pin Exposed Pad LQFP Development Board 2 ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit 3 OutV / SCLK OutEdge / DDR / 4 SDATA DCLK_RST/ 15 DCLK_RST- 30 CAL 29 PDQ 14 FSR/ECE Description Output Voltage Amplitude ...
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Pin Functions Pin No. Symbol CalDly / DES / 127 SCS 18 CLK+ 19 CLK I− Q− CMO ...
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Pin Functions Pin No. Symbol Equivalent Circuit R 32 EXT 34 Tdiode_P 35 Tdiode_N Description External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1. Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be ...
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Pin Functions Pin No. Symbol DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− DI5+ / ...
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Pin Functions Pin No. Symbol Equivalent Circuit 42, 53, 64, 74, 87, 97, DR GND 108, 119 52, 63, 98, NC 109, 120 Description Ground return for Connection. Make no connection to these pins. 7 www.national.com ...
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... Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Difference Voltage on Any Input Pin (Except Voltage (Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) ≤ ...
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Symbol Parameter Signal-to-Noise Plus Distortion SINAD Ratio SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion Out of Range Output Code (In addition to OR ...
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Symbol Parameter Analog Input Capacitance, Normal operation (Notes 10, 11 Analog Input Capacitance, DES Mode (Notes 10, 11) R Differential Input Resistance IN ANALOG OUTPUT CHARACTERISTICS V Common Mode Output Voltage CMO V input threshold to set DC ...
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Symbol Parameter V LVDS Differential Output Voltage OD Change in LVDS Output Swing Δ DIFF Between Logic Levels Output Offset Voltage, see Figure Output Offset Voltage, see Figure Output Offset Voltage Change ...
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Symbol Parameter Differential High to Low Transition t HLT Time t DCLK to Data Output Skew OSK t Data to DCLK Set-Up Time SU t DCLK to Data Hold Time H t Sampling (Aperture) Delay AD t Aperture Jitter AJ ...
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Note 7: To guarantee accuracy required that V achieving rated performance requires that the backside exposed pad be well grounded. Note 8: Typical figures are 25°C, and represent most likely parametric norms. Test limits are ...
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Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode the aperture ...
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one- half the sampling frequency, ...
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Timing Diagrams www.national.com FIGURE 3. ADC08D1000 Timing — SDR Clocking FIGURE 4. ADC08D1000 Timing — DDR Clocking 16 20097414 20097459 ...
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FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low 17 20097419 20097420 20097423 www.national.com ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing www.national.com 18 20097424 20097425 ...
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Typical Performance Characteristics INL vs. CODE DNL vs. CODE POWER DISSIPATION vs. SAMPLE RATE V =V =1.9V, F =1000MHz CLK INL vs. TEMPERATURE 20097464 DNL vs. TEMPERATURE 20097466 ENOB vs. CLOCK DUTY CYCLE 20097481 19 =25°C unless ...
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ENOB vs. TEMPERATURE ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE www.national.com ENOB vs. SUPPLY VOLTAGE 20097476 ENOB vs. INPUT FREQUENCY 20097478 SNR vs. SUPPLY VOLTAGE 20097468 20 20097477 20097479 20097469 ...
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SNR vs. SAMPLE RATE 20097470 THD vs. TEMPERATURE 20097472 THD vs. SAMPLE RATE 20097474 SNR vs. INPUT FREQUENCY THD vs. SUPPLY VOLTAGE THD vs. INPUT FREQUENCY 21 20097471 20097473 20097475 www.national.com ...
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SFDR vs. TEMPERATURE SFDR vs. SAMPLE RATE Spectral Response at FIN = 248 MHz www.national.com SFDR vs. SUPPLY VOLTAGE 20097485 SFDR vs. INPUT FREQUENCY 20097482 Spectral Response at FIN = 498 MHz 20097487 22 20097484 20097483 20097488 ...
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CROSSTALK vs. SOURCE FREQUENCY STEP RESPONSE FULL POWER BANDWIDTH 20097463 STEP RESPONSE DETAIL VIEW 20097461 23 20097486 20097462 www.national.com ...
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Functional Description The ADC08D1000 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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Control Modes Much of the user control can be accomplished with several control pins that are provided. Examples include initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08D1000 also provides an Extend- ...
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OutEdge Setting To help ease data capture in the SDR mode, the output data may be caused to transition on either the positive or the neg- ative edge of the output data clock (DCLK). This is chosen with the ...
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Feature SDR or DDR Clocking DDR Clock Phase SDR Data transitions with rising or falling DCLK edge LVDS output level Power-On Calibration Delay Full-Scale Range Input Offset Adjust Dual Edge Sampling Selection Dual Edge Sampling Input Channel Selection DES Sampling ...
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These 12 bits form the header. The next 4 bits are the address of the register that written to and the last 16 bits are the data written ...
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Sign Bits 15:8 Offset Value. The input offset of the I-Channel ADC is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero offset, ...
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Bit 15 DES Enable. Setting this bit to 1b enables the Dual Edge Sampling mode. In this mode the ADCs in this device are used to sample and convert the same analog input in a time- interleaved manner, accomplishing a ...
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FIGURE 10. Extended Mode Offset Behavior 1.5 MULTIPLE ADC SYNCHRONIZATION The ADC08D1000 has the capability to precisely reset its sampling clock input to DCLK output relationship as deter- mined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a ...
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FIGURE 11. Differential Input Drive When the d.c. coupled mode is used, a common mode volt- age must be provided at the differential inputs. This common mode voltage should track the V CMO V output potential will change with temperature. ...
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The LMH6555 of Figure 12 is suitable for any Full Scale Range. 2.3 THE CLOCK INPUTS The ADC08D1000 has differential LVDS clock inputs, CLK+ and CLK-, which must be driven with an a.c. coupled, differ- ential clock signal. Although the ...
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On-Command Calibration On-command calibration may be run at any time in NORMAL (non-DES) mode only. Do not run a calibration while operat- ing the ADC in Auto DES Mode. If the ADC is operating in Auto DES mode and ...
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ADC08D1000 is used is noisy, it may be necessary to tie the OutV pin high. 2.4.5 Dual Edge Sampling IMPORTANT NOTE: When using the ADC in Extended Con- trol Mode, the ...
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AD- C08D1000 power pins. The Absolute Maximum Ratings should be strictly observed, even during power up and power down. A power supply that produces a voltage spike at ...
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ADC08D1000 die of θ typical power consumption = 2.8 x 1.6 = 4.5°C. Allowing for a 5.5°C (including an extra 1°C) temperature drop from the die to the temperature sensor, then, would mean that maintaining a ...
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It is not uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground. Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance should control overshoot. ...
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Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead Exposed Pad LQFP Order Number ADC08D1000CIYB NS Package Number VNX128A 39 www.national.com ...
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