ADC10D1000RB/NOPB National Semiconductor, ADC10D1000RB/NOPB Datasheet
ADC10D1000RB/NOPB
Specifications of ADC10D1000RB/NOPB
Related parts for ADC10D1000RB/NOPB
ADC10D1000RB/NOPB Summary of contents
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... Ordering Information Industrial Temperature Range (-40°C < T ADC10D1000/1500CIUT/NOPB ADC10D1000/1500CIUT ADC10D1000/1500RB If Military/Aerospace specified devices are required, please contract the National Semiconductor Sales Office/Dis- tributors for availability and specifications. IBIS models are available at: http://www.national.com/analog/adc/ ibis_models. © 2011 National Semiconductor Corporation ADC10D1000/ADC10D1500 2.0 Features ■ ...
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Block Diagram www.national.com FIGURE 1. Simplified Block Diagram 2 30066353 ...
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General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................................................................................................................................... 1 5.0 Ordering Information ....................................................................................................................... 1 6.0 Block Diagram ................................................................................................................................ 2 7.0 Connection Diagram ........................................................................................................................ 6 8.0 Ball Descriptions and Equivalent Circuits ............................................................................................ ...
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Out-Of-Range Indication .............................................................................................. 53 17.1.6 Maximum Input Range ................................................................................................ 53 17.1.7 AC-coupled Input Signals ............................................................................................ 53 17.1.8 DC-coupled Input Signals ............................................................................................ 53 17.1.9 Single-Ended Input Signals .......................................................................................... 53 17.2 THE CLOCK INPUTS ........................................................................................................... 54 17.2.1 CLK Coupling ............................................................................................................. 54 ...
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TABLE 1. Analog Front-End and Clock Balls ................................................................................................... 7 TABLE 2. Control and Status Balls .............................................................................................................. 10 TABLE 3. Power and Ground Balls .............................................................................................................. 13 TABLE 4. High-Speed Digital Outputs .......................................................................................................... 14 TABLE 5. Package Thermal Resistance ........................................................................................................ 16 TABLE ...
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Connection Diagram The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Section 17.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS www.national.com FIGURE 2. ADC10D1000/1500 Connection Diagram 6 30066301 for ...
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Ball Descriptions and Equivalent Circuits Ball No. Name H1/J1 VinI+/- N1/M1 VinQ+/- U2/V1 CLK+/- V2/W1 DCLK_RST+/- TABLE 1. Analog Front-End and Clock Balls Equivalent Circuit 7 Description Differential signal I- and Q-inputs. In the Non-Du- al Edge Sampling (Non-DES) ...
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Ball No. Name V C2 CMO C3/D3 Rext+/- C1/D2 Rtrim+/- E2/F3 Tdiode+/- www.national.com Equivalent Circuit Description Common Mode Voltage Output or Signal Coupling Select. If AC-coupled operation at the analog inputs is desired, this pin should be ...
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Ball No. Name Y4/W5 RCLK+/- Y5/U6 RCOut1+/- V6/V7 RCOut2+/- Equivalent Circuit Description Reference Clock Input. When the AutoSync feature is active, and the ADC10D1000/1500 is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. ...
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Ball No. Name V5 DES V4 CalDly D6 CAL B5 CalRun www.national.com TABLE 2. Control and Status Balls Equivalent Circuit Description Dual Edge Sampling (DES) Mode select. In the Non-Extended Control Mode (Non-ECM), when this input is set to logic-high, ...
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Ball No. Name U3 PDI V3 PDQ A4 TPM A5 NDM Y3 FSR W4 DDRPh Equivalent Circuit Description Power Down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q-channel. Setting either input to logic-low ...
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Ball No. Name B3 ECE C4 SCS C5 SCLK B4 SDI A3 SDO D1, D7, E3, F4, DNC W3 www.national.com Equivalent Circuit Description Extended Control Enable bar. Extended feature control through the SPI interface is enabled when ...
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Ball No. Name A2, A6, B6, C6, D8, D9, E1, F1, V H4, N4, R1, T1, A U8, U9, W6, Y2, Y6 G1, G3, G4, H2, J3, K3, L3, M3 N2, P1, P3, P4, R3, R4 A11, A15, ...
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Ball No. Name K19/K20 DCLKI+/- L19/L20 DCLKQ+/- K17/K18 ORI+/- L17/L18 ORQ+/- www.national.com TABLE 4. High-Speed Digital Outputs Equivalent Circuit Description Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output ...
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Ball No. Name J18/J19 DI9+/- H19/H20 DI8+/- H17/H18 DI7+/- G19/G20 DI6+/- G17/G18 DI5+/- F18/F19 DI4+/- E19/E20 DI3+/- D19/D20 DI2+/- D18/E18 DI1+/- C19/C20 DI0+/- · · M18/M19 DQ9+/- N19/N20 DQ8+/- N17/N18 DQ7+/- P19/P20 DQ6+/- P17/P18 DQ5+/- R18/R19 DQ4+/- T19/T20 DQ3+/- U19/U20 ...
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Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage ( Supply Difference max(V )- A/TC/DR/E min(V ) A/TC/DR/E Voltage on Any Input Pin (except V +/-) IN V ...
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TABLE 7. Dynamic Converter Characteristics Symbol Parameter FPBW Full Power Bandwidth Gain Flatness CER Code Error Rate NPR Noise Power Ratio 1:2 Demux Non-DES Mode ENOB Effective Number of Bits SINAD Signal-to-Noise Plus Distortion Ratio SNR Signal-to-Noise Ratio THD Total ...
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Symbol Parameter 12) Non-Demux Non-DES Mode(Note ENOB Effective Number of Bits SINAD Signal-to-Noise Plus Distortion Ratio SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free Dynamic Range www.national.com ADC10D1000 Conditions ...
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Symbol Parameter DES Mode (Demux and Non-Demux Modes, Q-input only) ENOB Effective Number of Bits SINAD Signal-to-Noise Plus Distortion Ratio SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free Dynamic ...
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TABLE 8. Analog Input/Output and Reference Characteristics Symbol Parameter Analog Inputs V Analog Differential Input Full Scale IN_FSR Range C Analog Input Capacitance, IN Non-DES Mode (Note Analog Input Capacitance, DES Mode (Note 10) R Differential Input Resistance IN Common ...
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TABLE 9. I-Channel to Q-Channel Characteristics Symbol Parameter Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I, Q) X-TALK Crosstalk from I-channel (Aggressor) to Q-channel (Victim) Crosstalk from Q-channel (Aggressor) to I-channel (Victim) TABLE 10. Sampling Clock Characteristics ...
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TABLE 11. Digital Control and Output Pin Characteristics Symbol Parameter Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS) V Logic High Input Voltage IH V Logic Low Input Voltage IL I Input ...
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TABLE 12. Power Supply Characteristics Symbol Parameter I Analog Supply Current A I Track-and-Hold and Clock Supply TC Current I Output Driver Supply Current DR I Digital Encoder Supply Current E I Total Supply Current TOTAL ADC10D1000 Conditions Typ 1:2 ...
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Symbol Parameter P Power Consumption C TABLE 13. AC Electrical Characteristics Symbol Parameter Sampling Clock (CLK) f Maximum Sampling Clock CLK (max) Frequency f Minimum Sampling Clock CLK (min) Frequency Sampling Clock Duty Cycle t Sampling Clock Low Time CL ...
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Symbol Parameter t Latency in 1:2 Demux Non-DES LAT Mode (Note 10) Latency in 1:4 Demux DES Mode (Note 10) Latency in Non-Demux Non-DES Mode (Note 10) Latency in Non-Demux DES Mode (Note 10) t Over Range Recovery Time ORR ...
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These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case. Note 4: Human body model is ...
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Specification Definitions APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device the variation in aperture ...
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SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ- ence, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that ...
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Transfer Characteristic FIGURE 4. Input / Output Transfer Characteristic 29 30066322 www.national.com ...
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Timing Diagrams www.national.com FIGURE 5. Clocking in 1:2 Demux Non-DES Mode* FIGURE 6. Clocking in Non-Demux Non-DES Mode* 30 30066359 30066360 ...
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FIGURE 8. Clocking in Non-Demux Mode DES Mode* * The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the ...
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FIGURE 10. Power-on and On-Command Calibration Timing www.national.com FIGURE 9. Data Clock Reset Timing (Demux Mode) FIGURE 11. Serial Interface Timing 32 30066320 30066325 30066319 ...
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Typical Performance Plots 1.9V 1.0/1.5 GHz CLK Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 5 ...
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DNL vs. TEMPERATURE (ADC10D1000) ENOB vs. TEMPERATURE (ADC10D1000) ENOB vs. SUPPLY VOLTAGE (ADC10D1000) www.national.com DNL vs. TEMPERATURE (ADC10D1500) 30066341 ENOB vs. TEMPERATURE (ADC10D1500) 30066376 ENOB vs. SUPPLY VOLTAGE (ADC10D1500) 30066377 34 30066352 30066354 30066355 ...
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ENOB vs. CLOCK FREQUENCY (ADC10D1000) ENOB vs. INPUT FREQUENCY (ADC10D1000) ENOB vs. V (ADC10D1000) CMI ENOB vs. CLOCK FREQUENCY (ADC10D1500) 30066378 ENOB vs. INPUT FREQUENCY (ADC10D1500) 30066379 ENOB vs. V 30066342 35 30066356 30066357 (ADC10D1500) CMI 30066358 www.national.com ...
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SNR vs. TEMPERATURE (ADC10D1000) SNR vs. SUPPLY VOLTAGE (ADC10D1000) SNR vs. CLOCK FREQUENCY (ADC10D1000) www.national.com SNR vs. TEMPERATURE (ADC10D1500) 30066368 SNR vs. SUPPLY VOLTAGE (ADC10D1500) 30066369 SNR vs. CLOCK FREQUENCY (ADC10D1500) 30066370 36 30066311 30066315 30066316 ...
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SNR vs. INPUT FREQUENCY (ADC10D1000) THD vs. TEMPERATURE (ADC10D1000) THD vs. SUPPLY VOLTAGE (ADC10D1000) SNR vs. INPUT FREQUENCY (ADC10D1500) 30066371 THD vs. TEMPERATURE (ADC10D1500) 30066372 THD vs. SUPPLY VOLTAGE (ADC10D1500) 30066373 37 30066317 30066318 30066321 www.national.com ...
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THD vs. CLOCK FREQUENCY (ADC10D1000) THD vs. INPUT FREQUENCY (ADC10D1000) SFDR vs. TEMPERATURE (ADC10D1000) www.national.com THD vs. CLOCK FREQUENCY (ADC10D1500) 30066374 THD vs. INPUT FREQUENCY (ADC10D1500) 30066375 SFDR vs. TEMPERATURE (ADC10D1500) 30066385 38 30066395 30066323 30066324 ...
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SFDR vs. SUPPLY VOLTAGE (ADC10D1000) SFDR vs. CLOCK FREQUENCY (ADC10D1000) SFDR vs. INPUT FREQUENCY (ADC10D1000) SFDR vs. SUPPLY VOLTAGE (ADC10D1500) 30066384 SFDR vs. CLOCK FREQUENCY (ADC10D1500) 30066382 SFDR vs. INPUT FREQUENCY (ADC10D1500) 30066383 39 30066328 30066361 30066362 www.national.com ...
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SPECTRAL RESPONSE AT FIN = 248 MHz (ADC10D1000) SPECTRAL RESPONSE AT FIN = 498 MHz (ADC10D1000) CROSSTALK vs. SOURCE FREQUENCY (ADC10D1000) www.national.com SPECTRAL RESPONSE AT FIN = 373 MHz (ADC10D1500) 30066387 SPECTRAL RESPONSE AT FIN = 748 MHz (ADC10D1500) 30066388 ...
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FULL POWER BANDWIDTH (ADC10D1000 -12 NON-DES MODE DES MODE DESIQ MODE -15 0 1000 2000 INPUT FREQUENCY (MHz) POWER CONSUMPTION vs. CLOCK FREQUENCY (ADC10D1000) NPR vs. RMS NOISE LOADING LEVEL (ADC10D1000) FULL POWER BANDWIDTH (ADC10D1500) 0 ...
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NPR SPECTRAL RESPONSE (ADC10D1000) www.national.com 30066333 42 ...
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Functional Description The ADC10D1000/1500 is a versatile A/D converter with an innovative architecture which permits very high speed oper- ation. The controls available ease the application of the de- vice to circuit solutions. Optimum performance requires adherence to the ...
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This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Section 16.3.2.5 Demux/Non- demux Mode for more information. 16.2.1.3 Dual Data Rate Phase Pin (DDRPh) The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC10D1000/1500 ...
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Extended Control Mode In Extended Control Mode (ECM), most functions are con- trolled via the Serial Interface. In addition to this, several of the control pins remain active. See Table 17 is selected by setting the ECE Pin to ...
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FIGURE 13. Serial Data Protocol - Write Operation 46 30066393 ...
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FEATURES The ADC10D1000/1500 offers many features to make the device convenient to use in a wide variety of applications. Feature Selected via V AC/DC-coupled Mode Selection Selected via FSR Input Full-scale Range Adjust Input Offset Adjust Setting LC Filter ...
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Input Control and Adjust There are several features and configurations for the input of the ADC10D1000/1500 so that it may be used in many dif- ferent applications. This section covers AC/DC-coupled Mode, input full-scale range adjust, input offset adjust, ...
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GHz to 1.5 GHz; see Table 18. TABLE 18. LC Filter Code vs. f LCF(7:0) LCF(7:0) 0 0000 0000b 1 0000 0001b 2 0000 0011b 3 0000 0111b 4 ...
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TABLE 20. Test Pattern by Output Port in Demux Mode Time ORQ ORI Comments T0 000h 001h 002h 004h T1 3FFh 3FEh 3FDh 3FBh T2 000h 001h 002h 004h T3 3FFh 3FEh 3FDh 3FBh T4 000h ...
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On-command Calibration In addition to the power-on calibration recommended to execute an on-command calibration whenever the settings or conditions to the device are altered significantly, in order to obtain optimal parametric performance. Some examples in- clude: changing ...
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Applications Information 17.1 THE ANALOG INPUTS The ADC10D1000/1500 will continuously convert any signal which is present at the analog inputs, as long as a CLK signal is also provided to the device. This section covers important aspects related to ...
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FSR and the Reference Voltage The full-scale analog differential input range (V ADC10D1000/1500 is derived from an internal 1.254V bandgap reference. In Non-ECM, this full-scale range has two settings controlled by the FSR Pin; see Scale Input Range Pin ...
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The range of this termination resistor is specified as R 17.2 THE CLOCK INPUTS The ADC10D1000/1500 has a differential clock input, CLK+ and CLK-, which must be driven with an AC-coupled, differ- ential clock signal. ...
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Demux Mode and cap- ture data from just one 10-bit bus, e.g. just DI (or DId) although both DI and DId are fully operational. This will decimate the data by two and effectively ...
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In order to synchronize the DCLK (and Data) outputs of mul- tiple ADCs, the DCLKs must transition at the same time, as well phase with one another. The DCLK at each ADC is generated from the CLK ...
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FIGURE 21. Power and Grounding Example 57 30066302 www.national.com ...
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Thermal Management The Heat Slug Ball Grid Array (HSBGA) package is a modified version of the industry standard plastic BGA (Ball Grid Array) package. Inside the package, a copper heat spreader cap is The center balls are connected to ...
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ADC and t will be a known quantity. For CalDly the purpose of this section assumed that CalDly is set as recommended. ...
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FIGURE 25. Power-on with Control Pins set by FPGA post Power-on Cal 17.6.2 Power-on and Data Clock (DCLK) Many applications use the DCLK output for a system clock. For the ADC10D1000/1500, each I- and Q-channel has its own DCLKI and ...
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FIGURE 27. Typical Temperature Sensor Application 17.7.2 Clocking Device The clock source can be a PLL/VCO device such as the LMX2531LQxxxx family of products. The specific device should be selected according to the desired ADC sampling clock frequency. The ADC10D1000/1500RB ...
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Register Definitions Ten read/write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset ...
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Configuration Register 1 Addr: 0h (0000b) Bit Name CAL DPS OVS TPM POR Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit ...
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I-channel Offset Adjust Addr: 2h (0010b Bit Res OS Name POR Bits 15:13 Reserved. Must be set to 0b. Bit 12 OS: Offset Sign. The default setting of 0b incurs a positive ...
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Bit 15 Reserved. Must be set as shown. Bit 14 CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values selects the following calibration sequence: do not reset ...
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Reserved Addr: 9h (1001b Bit Name POR Bits 15:0 Reserved. Must be set as shown. Q-channel Offset Adjust Addr: Ah (1010b) Bit Res OS Name ...
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Aperture Delay Coarse Adjust Addr: Ch (1100b) Bit Name POR Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK ...
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Aperture Delay Fine Adjust and LC Filter Adjust Addr: Dh (1101b) Bit Name FAM(5:0) POR Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that ...
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Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAL-2. inches (millimeters) unless otherwise noted 292-Ball BGA Thermally Enhanced Package Order Number ADC10D1000/1500CUIT NS Package Number UFH292A 69 www.national.com ...
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