LM48822TLEVAL National Semiconductor, LM48822TLEVAL Datasheet - Page 9

• Manufacturer Part Number: LM48822TLEVAL
• Description: BOARD EVAL FOR LM48822TL
• Manufacturer: National Semiconductor
• Series: Boomer®r

Specifications of LM48822TLEVAL

• Amplifier Type: Class AB
• Output Type: Headphones, 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 40mW x 2 @ 32 Ohm
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Board Type: Fully Populated
• Utilized Ic / Part: LM48822
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Information
I
The LM48822 is controlled through an I
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open collector). The LM48822 and the master
can communicate at clock rates up to 400kHz.
the I
be stable during the HIGH period of SCL. The LM48822 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition
3. Each data word, device address and data, transmitted over
the bus is 8 bits long as is always followed by an acknowledge
pulse (Figure 4). The LM48822 device address is 1100000.
I
The I
the transition of SDA from HIGH to LOW while SDA is HIGH,
2
2
C COMPATIBLE INTERFACE
C BUS FORMAT
2
2
C interface timing diagram. Data on the SDA line must
C bus format is shown in
Figure
4. The START signal,
2
C compatible serial
Figure 2
FIGURE 4. Example I
FIGURE 3. Start and Stop Diagram
FIGURE 2. I
shows
Figure
2
C Timing Diagram
9
2
is generated, altering all devices on the bus that a device ad-
dress is being written to the bus.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the
master is writing to the slave device, R/W = 1 indicates the
master wants to read data from the slave device. The
LM48822 is a WRITE-ONLY device and will not respond the
R/W = 1. The data is latched in on the rising edge of the clock.
Each address bit must be stable while SDA is HIGH. After the
last address bit is transmitted, the master device releases
SDA, during which time, an acknowledge clock pulse is gen-
erated by the slave device. If the LM48822 receives the
correct address, the device pulls the SDA line low, generating
and acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. After the 8-bit register data word is sent, the
LM48822 sends another ACK bit. Following the acknowl-
edgement of the register data word, the master issues a
STOP bit, allowing SDA to go high while SDA is high.
C Write Cycle
30061002
30061001
30061014
www.national.com