MAX97001EVKIT+ Maxim Integrated Products, MAX97001EVKIT+ Datasheet - Page 31

• Manufacturer Part Number: MAX97001EVKIT+
• Description: KIT EVALUATION FOR MAX97001
• Manufacturer: Maxim Integrated Products

Specifications of MAX97001EVKIT+

• Description/function: Audio Amplifiers
• Operating Supply Voltage: 2.7 V to 5.5 V
• Product: Audio Development Tools
• Supply Current: 1 A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MAX97001

The MAX97001 recognizes a STOP condition at any
point during data transmission except if the STOP condi-
tion occurs in the same high pulse as a START condition.
For proper operation, do not send a STOP condition dur-
ing the same SCL high pulse as the START condition.
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the read/write bit. For
the MAX97001 the 7 MSBs are 1001101. Setting the
read/write bit to 1 (slave address = 0x9B) configures the
MAX97001 for read mode. Setting the read/write bit to 0
(slave address = 0x9A) configures the MAX97001 for write
mode. The address is the first byte of information sent to
the MAX97001 after the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that
the MAX97001 uses to handshake receipt each byte
of data when in write mode (Figure 9). The MAX97001
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX97001 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not-acknowledge is
Figure 9. Acknowledge
Audio Subsystem with Mono Class D Speaker
SDA
SCL
CONDITION
Early STOP Conditions
START
and Class H Headphone Amplifiers
Slave Address
Acknowledge
1
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NOT ACKNOWLEDGE
sent when the master reads the final byte of data from
the MAX97001, followed by a STOP condition.
A write to the MAX97001 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a STOP
condition. Figure 10 illustrates the proper frame format
for writing one byte of data to the MAX97001. Figure 11
illustrates the frame format for writing n-bytes of data to
the MAX97001.
The slave address with the R/W bit set to 0 indicates that
the master intends to write data to the MAX97001. The
MAX97001 acknowledges receipt of the address byte
during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the MAX97001’s internal register address pointer. The
pointer tells the MAX97001 where to write the next byte
of data. An acknowledge pulse is sent by the MAX97001
upon receipt of the address pointer data.
The third byte sent to the MAX97001 contains the
data that is written to the chosen register. An acknowl-
edge pulse from the MAX97001 signals receipt of the
data byte. The address pointer autoincrements to the
next register address after each received data byte.
This autoincrement feature allows a master to write to
sequential registers within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x09
are reserved. Do not write to these addresses.
ACKNOWLEDGE
ACKNOWLEDGMENT
CLOCK PULSE FOR
9
Write Data Format
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