NCP1203GEVB ON Semiconductor, NCP1203GEVB Datasheet - Page 10

• Manufacturer Part Number: NCP1203GEVB
• Description: EVAL BOARD FOR NCP1203G
• Manufacturer: ON Semiconductor

Specifications of NCP1203GEVB

• Design Resources: NCP1203GEVB BOM NCP1203GEVB Gerber Files NCP1203 EVB Schematic
• Main Purpose: AC/DC, Primary Side
• Outputs And Type: 1, Isolated
• Voltage - Output: 19V
• Current - Output: 4A
• Voltage - Input: 85 ~ 230VAC
• Regulator Topology: Flyback
• Frequency - Switching: 60kHz
• Board Type: Fully Populated
• Utilized Ic / Part: NPC1200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: NCP1203G
• Other names: NCP1203GEVBOS

Calculating the V
depends upon the V
V
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 11.4 V
to 9.8 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a V
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 1.5 mA, we can calculate
the required capacitor using the following formula:
C equals 8 mF or 10 mF for a standard value. When an
overload condition occurs, the IC blocks its internal
circuitry and its consumption drops to 350 mA typical. This
appends at V
reaches 6.5 V: we are in latchoff phase. Again, using the
calculated 10 mF and 350 mA current consumption, this
latchoff phase lasts: 109 ms.
Dt + DV @ C
CC
As the above section describes, the fall down sequence
line to go from 11.4 V to 9.8 V? The required time
Figure 20. If the fault is relaxed during the V
If the fault persists when V
i
, with DV = 2V. Then for a wanted Dt of 10 ms,
CC
CC
= 9.8 V and it remains stuck until V
CC
fall time of 10 ms could be well
CC
level: how long does it take for the
Capacitor
11.4 V
9.8 V
6.3 V
Internal
Fault
Flag
V
Drv
CC
CC
Startup Phase
reached UVLO
Occurs Here
Regulation
Pulses
Driver
http://onsemi.com
CC
natural fall down sequence, the IC automatically resumes.
L
CC
, then the controller cuts everything off until recovery.
10
Fault Occurs Here
Latchoff
Phase
Protecting the Controller Against Negative Spikes
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if they are a low impedance
path is offered between V
pin is often the seat of such spurious signals, the
high−voltage pin can also be the source of problems in
certain circumstances. During the turn−off sequence, e.g.
when the user unplugs the power supply, the controller is still
fed by its V
ON and OFF with a peak current limited by Rsense.
Unfortunately, if the quality coefficient Q of the resonating
network formed by Lp and Cbulk is low (e.g. the MOSFET
Rdson + Rsense are small), conditions are met to make the
circuit resonate and thus negatively bias the controller. Since
we are talking about ms pulses, the amount of injected
charge (Q = I x t) immediately latches the controller which
brutally discharges its V
is of sufficient value, its stored energy damages the
controller. Figure 21 depicts a typical negative shot
occurring on the HV pin where the brutal V
testifies for latchup.
As with any controller built upon a CMOS technology, it
CC
Relaxed
Fault is
Pulses
Driver
capacitor and keeps activating the MOSFET
CC
CC
Time
Time
Time
capacitor. If this V
and GND. If the current sense
CC
CC
discharge
capacitor