IRDC3840 International Rectifier, IRDC3840 Datasheet - Page 14

• Manufacturer Part Number: IRDC3840
• Description: BOARD EVAL SYNC BUCK CONVERTER
• Manufacturer: International Rectifier

Specifications of IRDC3840

• Silicon Manufacturer: International Rectifier
• Kit Contents: Board
• Features: Compact, High Performance And Flexible Solution, 600kHz Frequency
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: Power Management -
• Rohs Compliant: No

Thermal Shutdown
Temperature sensing is provided inside IR3840.
The trip threshold is typically set to 140
trip threshold is exceeded, thermal shutdown
turns off both MOSFETs and discharges the soft
start capacitor.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20
shutdown threshold.
Output Voltage Sequencing
The
programmable sequencing options using Seq,
Enable and Power Good pins.
Fig. 8a. Simultaneous Power-up of the slave
06/18/09
Through these pins, voltage sequencing such as
simultaneous
implemented. Figure 8. shows simultaneous
sequencing
power-up, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
R
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
E
/R
F
IR3840
with respect to the master.
=R
C
/R
Simultaneous Powerup
D
configurations.
o
, therefore, the output voltage of
C hysteresis in the thermal
can
and
accommodate
sequential
Vo1
Vo2
In
simultaneous
o
C. When
can
user
be
RE
RF
1.5V <Vin<16V
Vo(master)
PGood
4.5V <Vcc<5.5V
1.5V <Vin<16V
4.5V <Vcc<5.5V
Power Good Output
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage is
compared to a fixed voltage. As soon as the Fb
voltage reaches 0.88*V
flags. This pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. Fig 9. shows the timing
diagram for the PGood function.
PGood
Fig. 8b. Application Circuit for Simultaneous
Seq
Vcc
Rt
SS/ SD
PGood
Seq
Vcc
Rt
SS/ SD
PGood
Sequencing
Enable
Gnd
Enable
Gnd
Vin
IR3840MPbF
PGnd
Vin
PGnd
OCSet
ref
Comp
Boot
OCSet
SW
Comp
Fb
, the Power Good signal
Boot
SW
Fb
RA
RC
RB
RD
14
Vo(master)
Vo(slave)