LM3489EVAL National Semiconductor, LM3489EVAL Datasheet - Page 13

• Manufacturer Part Number: LM3489EVAL
• Description: BOARD EVALUATION LM3489
• Manufacturer: National Semiconductor

Specifications of LM3489EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 3.3V
• Current - Output: 500mA
• Voltage - Input: 7 ~ 28V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: LM3489
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -
• Frequency - Switching: -

PCB Layout
The PCB board layout is very important in all switching regu-
lator designs. Poor layout can cause switching noise into the
feedback signal and generate EMI problems. For minimal in-
ductance, the wires indicated by heavy lines in schematic
diagram should be as wide and short as possible. Keep the
ground pin of the input capacitor as close as possible to the
anode of the catch diode. This path carries a large AC current.
The switching node, the node with the diode cathode, inductor
and FET drain should be kept short. This node is one of the
main sources for radiated EMI since it sees a large AC voltage
at the switching frequency. It is always a good practice to use
a ground plane in the design, particularly for high current ap-
plications.
The two ground pins, PGND and GND, should be connected
by as short a trace as possible. They can be connected un-
derneath the device. These pins are resistively connected
FIGURE 7. Typical Application Schematic for VOUT = 3.3V/500mA
13
internally by approximately 50Ω. The ground pins should be
tied to the ground plane, or to a large ground trace in close
proximity to both the FB divider and C
The gate pin of the external PFET should be located close to
the PGATE pin. However, if a very small FET is used, a re-
sistor may be required between PGATE pin and the gate of
the PFET to reduce high frequency ringing. Since this resistor
will slow down the PFET’s rise time, the current limit blanking
time should be taken into consideration (refer to Current Lim-
iting Operation). The feedback voltage signal line can be
sensitive to noise. Avoid inductive coupling with the inductor
or the switching node. The FB trace should be kept away from
those areas. Also, the orientation of the inductor can con-
tribute un-wanted noise coupling to the FB path. If noise
problems are observed it may be worth trying a different ori-
entation of the inductor and select the best for final component
placement.
OUT
grounds.
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