LM3205TLEV National Semiconductor, LM3205TLEV Datasheet - Page 4

• Manufacturer Part Number: LM3205TLEV
• Description: BOARD EVALUATION LM3205TL
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM3205TLEV

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 0.8 ~ 3.6V
• Current - Output: 650mA
• Voltage - Input: 2.7 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM3205
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
Board Layout Considerations
The LM3205 converts higher input voltage to lower output
voltage with high efficiency. This is achieved with an
inductor-based switching topology. During the first half of the
switching cycle, the internal PMOS switch turns on and the
input voltage is applied to the inductor in which the current
flows from P
inductor. During the second half cycle, the PMOS turns off
and the internal NMOS turns on. The inductor current con-
tinues to flow via the inductor from the device PGND line to
the output capacitor (C2) .
Referring to Figure 5, the LM3205 has two major current
loops where pulse and ripple current flow. The loop shown in
the left hand side is important because pulse current flows in
this path. In the loop on the right hand side, the current
waveform in this path is triangular. Pulse current has many
high-frequency components due to fast di/dt. Triangular
ripple current also has wide high-frequency components.
Board layout and circuit pattern design of these two loops
are key factors for reducing noise radiation and achieiving
www.national.com
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
National Semiconductor
Americas Customer
Support Center
Email: [e-mail]
Tel: [phone]
VDD
line to the output capacitor (C2) through the
FIGURE 5. Current Loop
National Semiconductor
Europe Customer Support Center
Deutsch Tel: [phone]
English
Français Tel: [phone]
Email: [e-mail]
Fax: [phone]
Tel: [phone]
20169810
2. A critical component is any component of a life support device
stable operation. Other lines, such as input and output ter-
minals are DC current, therefore pattern width (current ca-
pability) and DCR drop considerations are needed.
BOARD LAYOUT FLOW
1. Minimize C1, PV
2. Minimize L1, C2, SW and PGND loop. These traces also
3. The layout patterns should be placed on the component
4. Connect C1(-), C2(-) and PGND with wide GND pattern.
5. SGND should not be connect directly to PGND. Con-
6. V
7. FB line should be protected from noise. It is recom-
Note: The evaluation board shown in Figure 2 and Figure 3 for the LM3205
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
should be as wide and short as possible.
should be as wide and short as possible.
side of the PCB to minimize parasitic inductance and
resistance due to via-holes. SW to L1 path should be
routed between C2(+) and C2(-) land patterns. If vias are
used in these large current paths, multiple via-holes
should be used if possible.
This pattern should be short, so C1(-), C2(-), and PGND
are as close as possible. Then connect to a PCB com-
mon GND pattern with as many via-holes as possible.
necting these pins under the device should be avoided.
(If possible, connect SGND to the common port of C1(-),
C2(-) and PGND.)
ing these pins under the device should be avoided. It is
recommended to connect V
switching noise injection to the V
mended to use an inner GND layer (if available) as a
shield.
was designed with the considerations mentioned above, and it shows
good performance. However some aspects have not been optimized
because of limitations due to evaluation-specific requirements. The
board can be used as a reference. For specific questions, please refer
to a National representative.
DD
National Semiconductor
Asia Pacific Customer
Support Center
Email: [e-mail]
should not be connected directly to PV
IN
, and PGND loop. These traces
DD
National Semiconductor
Japan Customer Support Center
Fax: [phone]
Email: [e-mail]
Tel: [phone]
to the C1(+) to avoid
DD
line.
IN
. Connect-