LM2744EVAL National Semiconductor, LM2744EVAL Datasheet - Page 16

• Manufacturer Part Number: LM2744EVAL
• Description: BOARD EVALUATION LM2744
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM2744EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.2V
• Current - Output: 3.5A
• Voltage - Input: 1.8 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM2744
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -

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In the equation for f
sistance, and represents the inductor DCR plus the on resis-
tance of the high-side MOSFET. R
divided by output current. The power stage transfer function
G
Bode plots of the phase and gain in this example.
a = LC
b = L + C
c = R
PS
is given by the following equation, and Figure 12 shows
O
O
+ R
(R
O
O
(R
L
+ R
O
R
C
L
)
+ R
DP
O
, the variable R
R
C
+ R
C
R
L
)
O
L
is the power stage re-
is the output voltage
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The double pole at 4.5kHz causes the phase to drop to ap-
proximately -130° at around 10kHz. The ESR zero, at
20.3kHz, provides a +90° boost that prevents the phase from
dropping to -180º. If this loop were left uncompensated, the
bandwidth would be approximately 10kHz and the phase
margin 53°. In theory, the loop would be stable, but would
suffer from poor DC regulation (due to the low DC gain) and
would be slow to respond to load transients (due to the low
bandwidth.) In practice, the loop could easily become unsta-
ble due to tolerances in the output inductor, capacitor, or
changes in output current, or input voltage. Therefore, the
loop is compensated using the error amplifier and a few pas-
sive components.
For this example, a Type III, or three-pole-two-zero approach
gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including
Type III, a single pole is placed at the origin to boost DC gain
as high as possible. Two zeroes f
double pole frequency to cancel the double pole phase lag.
Then, a pole, f
A final pole f
The gain of the error amplifier transfer function is selected to
give the best bandwidth possible without violating the Nyquist
stability criteria. In practice, a good crossover point is one-fifth
of the switching frequency, or 60kHz for this example. The
generic equation for the error amplifier transfer function is:
In this equation the variable A
capacitance and resistance of the compensation compo-
nents, arranged as shown inFigure 12. A
provide the desired bandwidth. A starting value of 80,000 for
A
value will increase the bandwidth, but will also decrease
phase margin. Designs with 45-60° are usually best because
they represent a good tradeoff between bandwidth and phase
margin. In general, phase margin is lowest and gain highest
(worst-case) for maximum input voltage and minimum output
EA
should give a conservative bandwidth. Increasing the
FIGURE 12. Power Stage Gain and Phase
P2
is placed at one-half of the switching frequency.
P1
is placed at the frequency of the ESR zero.
EA
is a ratio of the values of the
Z1
and f
Z2
EA
are placed at the
is selected to
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