LM5026EVAL National Semiconductor, LM5026EVAL Datasheet - Page 18

• Manufacturer Part Number: LM5026EVAL
• Description: BOARD EVALUATION LM5026
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5026EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 30A
• Voltage - Input: 36 ~ 78V
• Regulator Topology: Buck
• Frequency - Switching: 230kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5026
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -

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good use of this feature. If the application requires no delay
from the first detection of a current limit condition to the onset
of the hiccup mode (t1 = 0), the RES pin can be left open (no
external capacitor). If it is desired to disable the hiccup mode
current limit operation, the RES pin should be connected to
ground (AGND).
SOFT-START (SS)
An internal current source and an external soft-start capacitor
determines the time required for the output duty cycle to in-
crease from zero to its final value for regulation. The minimum
acceptable time is dependent on the output capacitance and
the response of the feedback loop. If the soft-start time is too
quick, the output could overshoot its intended voltage before
the feedback loop can regulate the PWM controller. After
power is applied and the controller is fully enabled, the voltage
at the SS pin ramps up as C
µA current source. The voltage at the output of the COMP pin
current mirror is clamped to the same potential as the SS pin
by a voltage buffer with a sink-only output stage. When the
SS voltage reaches
output with very low duty cycle. The PWM duty cycle gradually
increases as the voltage at the SS pin charges to
VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE
As the input source V
pin increases proportionately. To limit the Volt x Seconds ap-
plied to the transformer, the maximum allowed PWM duty
cycle decreases as the UVLO voltage increases. If it is de-
sired to increase the slope of the voltage limited duty cycle
characteristic, two possible configurations are shown in
ure
the UVLO pin voltage to increase more rapidly with increasing
input voltage (V
cycle clamp varies with the UVLO pin voltage according to the
following equation:
Voltage-Dependent Duty Cycle (%) = 107 - 21.8 X UVLO
17. After the LM5026 is enabled, the zener diode causes
PWR
). The voltage dependent maximum duty
≈
PWR
1.4V, PWM pulses appear at the driver
increases the voltage at the UVLO
SS
is charged by an internal 50
≈
5.0V.
Fig-
18
Programmable Maximum Duty Cycle Clamp (DCL)
When the UVLO pin is biased at 1.25V (minimum operating
level), the maximum duty cycle of OUT_A is limited by the
duty cycle of the internal clock signal. The duty cycle of the
internal clock can be adjusted by programming a voltage set
at the DCL pin. The default maximum duty cycle (80%) can
be selected by connecting the DCL pin to the RT pin. The DCL
pin should not be left open. A small decoupling capacitor lo-
cated close to the DCL pin is recommended.
The oscillator frequency set resistance (R
mined first before programming the maximum duty cycle.
Following the selection of the total R
the R
duty cycle. As the UVLO pin voltage increases from 1.25V,
the maximum duty cycle is reduced by the voltage dependent
duty cycle limiter previously as described and illustrated in
Figure
Printed Circuit Board Layout
The LM5026 Current Sense and PWM comparators are very
fast, and respond to short duration noise pulses. The compo-
nents at the CS, COMP, SS, DCL, UVLO, TIME, SYNC and
the RT pins should be as physically close as possible to the
IC, thereby minimizing noise pickup on the PC board tracks.
FIGURE 17. Altering the Slope of Duty Cycle vs. V
T
resistors can be designed to set the desired maximum
6.
T
resistance, the ratio of
T
) must be deter-
PWR
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