AD9750-EB Analog Devices Inc, AD9750-EB Datasheet
AD9750-EB
Specifications of AD9750-EB
Related parts for AD9750-EB
AD9750-EB Summary of contents
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... The AD9750 is available in 28-lead SOIC and TSSOP packages specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9750 is a member of the wideband TxDAC high per- formance product family that provides an upward or downward component selection path based on resolution ( bits), performance and cost. The entire family of TxDACs is avail- able in industry standard pinouts ...
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... AD9750–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT ...
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... MHz CLOCK OUT NOTES 1 Measured single ended into 50 load. Specifications subject to change without notice. REV AVDD = +5 V, DVDD = + MIN MAX OUTFS 50 Doubly Terminated, unless otherwise noted) Min ) 125 –3– AD9750 = 20 mA, Differential Transformer Coupled Output, Typ Max 2.5 2 –80 –76 – ...
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... ST OR 0.1% Figure 1. Timing Diagram Max Units Model +6.5 V AD9750AR +6.5 V AD9750ARU – +85 C 28-Lead TSSOP +0.3 V AD9750-EB +6 Small Outline IC Thin Shrink Small Outline Package. DVDD + 0.3 V DVDD + 0.3 V THERMAL CHARACTERISTICS AVDD + 0.3 V Thermal Resistance AVDD + 0.3 V 28-Lead 300 Mil SOIC AVDD + 0 ...
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... CLOCK DB8 2 27 DVDD 26 DB7 3 DCOM 4 DB6 25 NC DB5 5 24 AVDD AD9750 DB4 6 23 ICOMP TOP VIEW (Not to Scale) DB3 7 22 IOUTA DB2 8 21 IOUTB 9 20 DB1 ACOM DB0 ADJ REFIO 13 16 REFLO SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9750 ...
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... It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone For MIN MAX +5V REFLO AVDD ACOM 150pF AD9750 PMOS ICOMP CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB FOR DB9–DB1 SWITCH LATCHES ...
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... OUT 90 1MHz/5MHz 80 5MHz/25MHz 70 13MHz/65MHz 60 25MHz/125MHz 50 –25 –20 –15 –10 –5 A – dBc OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9750 = +25 C, SFDR up to Nyquist, unless otherwise noted 0dBF –6dBF S 60 –12dBF – MHz OUT Figure 5. SFDR vs MSPS OUT 90 20mAF ...
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... AD9750 0.2 0.15 0.1 0.05 0 –0.05 –0.1 1000 0 200 400 600 800 CODE Figure 12. Typical INL 125MSPS CLOCK – 13.5MHz OUT1 f = 14.5MHz OUT2 –20 AMPLITUDE = 0dBF S SDFR = 75dBc –30 –40 –50 –60 –70 –80 –90 –100 – MHz OUT Figure 15. Two-Tone SFDR ...
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... FUNCTIONAL DESCRIPTION Figure 17 shows a simplified block diagram of the AD9750. The AD9750 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... Figure 19. External Reference Configuration AVDD 1.2V AD1580 REFERENCE CONTROL AMPLIFIER The AD9750 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I The control amplifier is configured as a V-I converter as shown in Figure 19, such that its current output, I the ratio of the V in Equation 4 ...
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... The negative output compliance range of –1 set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9750. The positive output compliance range is slightly dependent on the full-scale output current, I ...
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... The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9750 as well as its required min/ max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise ...
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... Figure 27. I APPLYING THE AD9750 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9750. Unless otherwise noted assumed that I OUTFS ing the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration ...
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... In this case, AVDD which is the positive analog supply for both the AD9750 and the op amp is also used to level-shift the differ- ential output of the AD9750 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... PSRR of the DAC at 1 MHz, which Figure 33 becomes Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9750 fea- tures separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system ...
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... Analog Devices’ application notes AN-280 and AN-333. APPLICATIONS Using the AD9750 for Quadrature Amplitude Modulation (QAM) QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in FDM as well as spreadspectrum (i ...
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... RESISTOR NETWORK - TOMC1603-100D ACOM AD9750 EVALUATION BOARD General Description The AD9750- evaluation board for the AD9750 10-bit D/A converter. Careful attention to layout and circuit design combined with a prototyping area allow the user to easily and effectively evaluate the AD9750 in any application where high resolution, high speed conversion is required ...
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... AD9750 Figure 38. Evaluation Board Schematic –18– REV. 0 ...
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... REV. 0 Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) –19– AD9750 ...
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... AD9750 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) –20– REV. 0 ...
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... REV. 0 Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom –21– AD9750 ...
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... AD9750 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0 ...