LM3509SDEV National Semiconductor, LM3509SDEV Datasheet - Page 21

• Manufacturer Part Number: LM3509SDEV
• Description: BOARD EVALUATION FOR LM3509SD
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM3509SDEV

• Current - Output / Channel: 40mA
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 21V
• Features: Dimmable, I²C Interface
• Voltage - Input: 2.7 ~ 5.5V
• Utilized Ic / Part: LM3509
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OUTPUT CURRENT RANGE (OLED MODE)
The maximum output current the LM3509 can deliver in OLED
mode is limited by 4 factors (assuming continuous conduc-
tion); the peak current limit of 770mA (typical), the inductor
value, the input voltage, and the output voltage. Calculate the
maximum output current (I
tion:
For the typical application circuit with V
ing 70% efficiency, the maximum output current at V
will be approximately 70mA. At 4.2V due to the shorter on
times and lower average input currents the maximum output
current (at 70% efficiency) jumps to approximately 105mA.
Figure 11 shows a plot of I
equation, assuming 80% efficiency. In reality factors such as
current limit and efficiency will vary over V
component selection. This can cause the actual I
be higher or lower.
OUTPUT VOLTAGE RANGE (OLED MODE)
The LM3509's output voltage is constrained by 2 factors. On
the low end it is limited by the minimum duty cycle of 10%
(assuming continuous conduction) and on the high end it is
limited by the over voltage protection threshold (V
(typical). In order to maintain stability when operating at dif-
ferent output voltages the output capacitor and inductor must
be changed. Refer to Table 10 for different V
L combinations.
FIGURE 11. Typical Maximum Output Current in OLED
OUT_MAX
Mode
OUT_MAX
) using the following equa-
vs. V
OUT
IN
IN
= 18V and assum-
, temperature, and
using the above
OUT
30004362
, C
OVP
OUT_MAX
IN
OUT
) of 22V
= 2.7V
, and
to
21
TABLE 10. Component Values for
Output Voltage Selection
LAYOUT CONSIDERATIONS
The LLP is a leadless package with very good thermal prop-
erties. This package has an exposed DAP (die attach pad) at
the underside center of the package measuring 1.6mm x
2.0mm. The main advantage of this exposed DAP is to offer
low thermal resistance when soldered to the thermal ground
pad on the PCB. For good PCB layout a 1:1 ratio between the
package and the PCB thermal land is recommended. To fur-
ther enhance thermal conductivity, the PCB thermal ground
pad may include vias to a 2nd layer ground plane. For more
detailed instructions on mounting LLP packages, please refer
to National Semiconductor Application Note AN-1187.
The high switching frequencies and large peak currents make
the PCB layout a critical part of the design. The proceeding
steps must be followed to ensure stable operation and proper
current source regulation.
1, Divide ground into two planes, one for the return terminals
of C
of R
exposed PAD, but nowhere else.
2, Connect the inductor and the anode of D1 as close together
as possible and place this connection as close as possible to
the SW pin. This reduces the inductance and resistance of
the switching node which minimizes ringing and excess volt-
age drops. This will improve efficiency and decrease noise
that can get injected into the current sources.
3, Connect the return terminals of the input capacitor and the
output capacitor as close as possible to the exposed PAD and
through low impedance traces.
4, Bypass IN with at least a 1µF ceramic capacitor. Connect
the positive terminal of this capacitor as close as possible to
IN.
5, Connect C
This reduces the inductance and resistance of the output by-
pass node which minimizes ringing and the excess voltage
drops. This will improving efficiency and decrease noise that
can get injected into the current sources.
6, Route the traces for R
from the SW node to minimize noise injection.
7, Do not connect any external capacitance to the SET pin.
V
18V
15V
12V
OUT
SET
9V
7V
5V
OUT
, C
and the feedback network. Connect both planes to the
IN
and the I
OUT
as close as possible to the cathode of D1.
2.2µF
2.2µF
4.7µF
C
10µF
10µF
22µF
OUT
2
C Bus, the other for the return terminals
SET
and the feedback divider away
4.7µH
4.7µH
10µH
10µH
10µH
10µH
L
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V
IN
2.7V to
2.7V to
2.7V to
2.7V to
2.7V to
2.7V to
5.5V
5.5V
5.5V
5.5V
5.5V
4.5V
Range