LM3553SDEV National Semiconductor, LM3553SDEV Datasheet - Page 4

• Manufacturer Part Number: LM3553SDEV
• Description: BOARD EVALUATION FOR LM3553S
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM3553SDEV

• Current - Output / Channel: 1.2A
• Outputs And Type: 1, Non-Isolated
• Features: Camera Flash and Torch Modes, I²C Interface, Programmable Output Current
• Voltage - Input: 2.7 ~ 5.5V
• Utilized Ic / Part: LM3553
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Output: -

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will not boost to the required voltage and performance
will be degraded.
EXTERNAL CONTROL INTERFACE CONNECTION
The LM3553 Evaluation Board provides two ways to connect
an I
method to connect the interface is through a set of connectors
on the bottom of the evaluation board that allow the board to
plug into National's USB interface board directly. The second
method of interface connection is through a header strip lo-
cated on the left hand side of the evaluation board. There are
pins available to connect VIO (contoller reference voltage),
SCL (Interface Clock Line), and SDA (Interface Data Line)
each separated by a ground pin. The evaluation board has
two external pull-ups that connect both SCL and SDA to VIO
to compliment the open drain inputs found on the LM3553.
The OPERATION DESCRIPTION section of this application
note describes the internal registers and I
terface in greater detail.
OPERATION DESCRIPTION
I
DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, the state of the data
line can only be changed when CLK is LOW.
A pull-up resistor between VIO and SDA must be greater than
[ (VIO-V
Using a larger pull-up resistor results in lower switching cur-
rent with slower edges, while using a smaller pull-up results
in higher switching currents with faster edges.
2
C Compatible Interface
2
C compatible interface to the LM3553 IC. The first
OL
) / 3.7mA] to meet the V
FIGURE 5. Data Validity Diagram
OL
ack = acknowledge (SDA pulled down by the slave)
requirement on SDA.
2
C compatible in-
id = chip address, 53h for LM3553
FIGURE 7. Write Cycle
30049607
w = write (SDA = "0")
4
START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the
end of the I
signal transitioning from HIGH to LOW while SCL line is
HIGH. A STOP condition is defined as the SDA transitioning
from LOW to HIGH while SCL is HIGH. The I
generates START and STOP conditions. The I
sidered to be busy after a START condition and free after a
STOP condition. During data transmission, the I
can generate repeated START conditions. First START and
repeated START conditions are equivalent, function-wise.
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, the state of the data
line can only be changed when CLK is LOW.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The master releases the SDA line (HIGH) during the acknowl-
edge clock pulse. The LM3553 pulls down the SDA line during
the 9th clock pulse, signifying an acknowledge. The LM3553
generates an acknowledge after each byte has been re-
ceived.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LM3553 address
is 53h. For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
FIGURE 6. Start and Stop Conditions
2
C session. A START condition is defined as SDA
2
C master sends a chip ad-
30049615
2
C master always
2
C bus is con-
2
C master
30049614