CT-161-CD Fujitsu Semiconductor America Inc, CT-161-CD Datasheet
CT-161-CD
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CT-161-CD Summary of contents
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... FEATURES Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz). • Operation by sub-clock (8.192 kHz) is allowed. • Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multi- plied PLL clock) ...
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... Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin input. CAN controller: 1 channel • Compliant with Ver2.0A and Ver2.0B CAN specifications • ...
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... DTP/External interrupt: 4 channels, CAN wakeup: 1channel • Module for activation of expanded intelligent I/O service (EI Delay interrupt generator module • Generates interrupt request for task switching. 8/10-bit A/D converter: 8 channels • Resolution is selectable between 8-bit and 10-bit. • Activation by external trigger input is allowed. ...
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... Instruction length : 1 byte to 7 bytes Data bit length : 1 bit, 8 bits, 16 bits Minimum instruction execution time : 62.5 ns (at 16-MHz machine clock) Interrupt processing time : 1 minimum (at 16-MHz machine clock) Sleep mode/Clock mode/Time-base timer mode/ Stop mode/CPU intermittent General-purpose input/output ports (CMOS output ports (36 ports* ...
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... PACKAGE DIMENSION for details of the package. PRODUCT COMPARISON Memory space When testing with test product for evaluation, check the differences between the product and a product to be used actually. Pay attention to the following points: • The MB90V495G has no built-in ROM. However, a special-purpose development tool allows the operations as those of one with built-in ROM. ROM capacity depends on settings on a development tool. • ...
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MB90385 Series PIN ASSIGNMENT AV CC AVR P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P37/ADTG P20/TIN0 * : MB90387, MB90F387 MB90387S, MB90F387S: P36, P35 6 (TOP VIEW ...
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... Function as an event output pin for reload timer 0. Valid only when output setting is “enabled.” General-purpose input/output ports. Function as an event input pin for reload timer 1. Use the pin by setting as input port. General-purpose input/output ports. Function as an event output pin for reload timer 1. Valid only when output setting is “ ...
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... MB90387S, MB90F387S: P36, P35 8 Function General-purpose input/output ports. High-current output ports. Functions as output pin of PPG timers 01 and 23. Valid when output setting is “enabled.” General-purpose input/output port. Serial data input pin for UART. Use the pin by setting as input port. General-purpose input/output port. ...
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I/O CIRCUIT TYPE Type Circuit X1 X1A A X0 X0A Vcc Vcc Pch D Nch Vss R Standby control Vcc Pch E Nch Vss R Standby control Analog input MB90385 Series • High-rate oscillation feedback ...
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... High-current output Nch Vss Hysteresis input Standby control Remarks • Hysteresis input with pull-down resistor • Pull-down resistor, approx • FLASH product is not provided with pull-down resistor. • CMOS hysteresis input • CMOS level output (high-current output) • Standby control provided ...
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... Using external clock Notes When Using No Sub Clock • oscillator is not connected to X0A and X1A pin, apply pull-down resistor to X0A pin and leave X1A pin open. About Power Supply Pins • If two or more Vcc and Vss exist, the pins that should be at the same potential are connected to each other inside the device ...
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... For preventing malfunctions on built-in step-down circuit, maintain a minimum voltage rising time (between 0.2 V and 2.7V) when turning on the power. Stabilization of supply voltage • A sudden change in the supply voltage may cause the device to malfunction even within the specified V supply voltage operating range. Therefore, the V For reference, the supply voltage should be controlled so that V commercial frequencies ( Hz) fall below 10 of fluctuation does not exceed 0 ...
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BLOCK DIAGRAM X0,X1 Clock RST control circuit X0A,X1A Clock timer Time-base timer RAM ROM/FLASH Prescaler SOT1 UART1 SCK1 SIN1 AVcc AVss 8/10-bit A/D AN0 to AN7 converter (8ch) AVR ADTG MB90385 Series CPU F 2 MC-16LX core 16-bit free-run timer ...
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... H Note : When internal ROM is operating bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing table in ROM without specifying “far” using pointer. ...
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... Port 1 direction data register H 000012 DDR2 Port 2 direction data register H 000013 DDR3 Port 3 direction data register H 000014 DDR4 Port 4 direction data register H 000015 DDR5 Port 5 direction data register H 000016 H to 00001A H 00001B ADER Analog input permission register H 00001C H to 000025 H 000026 ...
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... PPG0/1 count clock selection 000042 PPG01 H register 000043 H PPG2 operation mode control 000044 PPGC2 H register PPG3 operation mode control 000045 PPGC3 H register PPG2/3 count clock selection 000046 PPG23 H register 000047 H to 00004F H 000050 H IPCP0 Input capture data register 0 000051 H 000052 H ...
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... H to 000065 H 000066 H TMCSR0 000067 H Timer control status register 000068 H TMCSR1 000069 H 00006A H to 00006E H ROM mirroring function selection 00006F ROMM H register 000070 H to 00007F H 000080 BVALR Message buffer enabling register H 000081 H 000082 TREQR Send request register H 000083 H 000084 ...
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... MB90385 Series Register Address abbreviation Lower power consumption mode 0000A0 LPMCR H control register 0000A1 CKSCR Clock selection register H 0000A2 H to 0000A7 H 0000A8 WDTC Watchdog timer control register H 0000A9 TBTC Time-base timer control register H 0000AA WTC Clock timer control register H 0000AB H to ...
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... Detection address setting register 0 001FF1 PADR0 H (middle-order) Detection address setting register 0 001FF2 H (high-order) Detection address setting register 1 001FF3 H (low-order) Detection address setting register 1 001FF4 PADR1 H (middle-order) Detection address setting register 1 001FF5 H (high-order) 003900 TMR0/ 16-bit timer register 0/16-bit reload H TMRLR0 ...
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MB90385 Series Register Address abbreviation 003C10 H to IDR0 ID register 0 003C13 H 003C14 H to IDR1 ID register 1 003C17 H 003C18 H to IDR2 ID register 2 003C1B H 003C1C H to IDR3 ID register 3 003C1F ...
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Register Address abbreviation 003C3C H DLCR6 DLC register 6 003C3D H 003C3E H DLCR7 DLC register 7 003C3F H 003C40 H to DTR0 Data register 0 003C47 H 003C48 H to DTR1 Data register 1 003C4F H 003C50 H to ...
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... H 003D0C RFWTR Remote frame receive wait register H 003D0D H Send completion interrupt 003D0E TIER H permission register 003D0F H 003D10 H AMSR Acceptance mask selection register 003D11 H 003D12 H 003D13 H 003D14 H to AMR0 Acceptance mask register 0 003D17 H 003D18 H to AMR1 Acceptance mask register 1 003D1B ...
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... INTERRUPT SOURCES, INTERRUPT VECTORS EI Interrupt source readiness Reset INT 9 instruction Exceptional treatment CAN controller reception completed (RX) CAN controller transmission completed (TX) / Node status transition (NS) Reserved Reserved CAN wakeup Time-base timer 16-bit reload timer 0 8/10-bit A/D converter 16-bit free-run timer overflow Reserved Reserved ...
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... Peripheral functions sharing an ICR register have the same interrupt level. If peripheral functions share an ICR register, only one function is available when using expanded intelligent I/O service. If peripheral functions share an ICR register, a function using expanded intelligent I/O service does not allow interrupt by another function Only 16-bit reload timer is ready for EI ...
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... I/O Ports The I/O ports are used as general-purpose input/output ports (parallel I/O ports). The MB60385 series model is provided with 5 ports (34 inputs). The ports function as input/output pins for peripheral functions also. I/O port functions An I/O port, using port data resister (PDR), outputs the output data to I/O pin and input a signal input to I/O port. ...
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... Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). Port 2 registers • Port 2 registers include port 2 data register (PDR2) and port 2 direction register (DDR2). • The bits configuring the register correspond to port 2 pins on a one-to-one basis. Relation between port 2 registers and pins ...
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... Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). Port 3 registers • Port 3 registers include port 3 data register (PDR3) and port 3 direction register (DDR3). • The bits configuring the register correspond to port 3 pins on a one-to-one basis. Relation between port 3 registers and pins ...
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... Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). Port 4 registers • Port 4 registers include port 4 data register (PDR4) and port 4 direction register (DDR4). • The bits configuring the register correspond to port 4 pins on a one-to-one basis. Relation between port 4 registers and pins ...
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... Standby control: Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). Port 5 registers • Port 5 registers include port 5 data register (PDR5), port 5 direction register (DDR5), and analog input per- mission register (ADER). • Analog input permission register (ADER) allows or disallows input of analog signal to the analog input pin. ...
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... The time-base time is an 18-bit free-run counter (time-base timer counter) that counts up in synchronization with the main clock (dividing main oscillation clock by 2). • Four choices of interval time are selectable, and generation of interrupt request is allowed for each interval time. • Provides operation clock signal to oscillation stabilizing wait timer and peripheral functions. ...
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... Time-base timer control register (TBTC) Time-base timer interrupt signal OF : Overflow HCLK : Oscillation clock *1 : Switch machine clock from main clock to PLL clock Switch machine clock from sub clock to main clock. Actual interrupt request number of time-base timer is as follows: Interrupt request number: #16 (10 To PPG timer ...
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... The interval time of a watchdog timer is determined by a clock cycle, which is input as a count clock. Watchdog resetting occurs between a minimum time and a maximum time specified. • The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the clock timer control register. ...
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... Shift to stop mode Time-base timer counter Main clock (dividing HCLK by 2) Clock counter Sub clock SCLK HCLK: Oscillation clock SCLK: Sub clock MB90385 Series Clock timer control register (WTC) SRST WTE WT1 WT0 WDCS 2 Activate Watchdog 2-bit Count clock counter generation selector Clear ...
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... Functions of input capture The input capture, upon detecting an edge of a signal input to the input pin from external device, stores a counter value of 16-bit free-run timer at the time of detection into the input capture data register. The function includes the input capture data registers corresponding to four input pins, input capture control status register, and edge detection circuit. • ...
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... Counter value of 16-bit free-run timer is used as reference time (base time) of input capture. Input capture Input capture detects rising edge, falling edge or both edges and retains a counter value of 16-bit free-run timer. Detection of edge on input signal is allowed to generate interrupt. 16-bit free-run timer block diagram ...
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MB90385 Series Detailed pin assignment on block diagram The 16-bit input/output timer includes a 16-bit free-run timer. Interrupt request number of the 16-bit free-run timer is as follows: Interrupt request number: 19 (13 Prescaler The prescaler divides a machine clock ...
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... ICP1 ICP0 ICP0 status register (ICS23) Input capture control ICP1 ICP0 status register (ICS01) IN1 Pin IN0 Pin Edge detection circuit 16-bit free-run timer Input capture data register 3 (IPCP3) Input capture data register 2 (IPCP2 ICE1 ICE1 ICE0 ICE0 EG11 EG11 EG10 ...
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... MB90385 series device has 2 channels of built-in 16-bit reload timer. Operation mode of 16-bit reload timer Count clock Internal clock mode Event count mode Internal clock mode • The 16-bit reload timer is set to internal clock mode, by setting count clock selection bit (TMCSR: CSL1, CSL0) to “00 ”, “01 ”, “10 ”. B ...
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... Count clock generation circuit Machine 3 Prescaler clock Clear Input control Pin circuit TIN External clock 3 Select function CSL1 CSL0 MOD2 MOD1 Timer control status register (TMCSR) Internal data bus Reload signal CLK Gate Valid input Wait signal clock decision circuit Output control ...
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... Clock Timer Outline The clock timer is a 15-bit free-run counter that increments in synchronization with sub clock. • Interval time is selectable among 7 choices, and generation of interrupt request is allowed for each interval. • Provides operation clock to the subclock oscillation stabilizing wait timer and watchdog timer. ...
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... Shift to hardware standby Shift to stop mode Clock time interrupt OF : Overflow SCLK : Sub clock Actual interrupt request number of clock timer is as follows : Interrupt request number : #28 (1C H Clock timer counter A 15-bit up counter that uses sub clock (SCLK count clock. Counter clear circuit A circuit that clears the clock timer counter. ...
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... The 8/-16-bit PPG timer is composed of four 8-bit reload register (PRLH0/PRLL0, PRLH1/PRLL1) and two PPG down counters (PCNT0, PCNT1). • Widths of “H” and “L” in output pulse are specifiable independently. Cycle and duty factor of output pulse is specifiable arbitrarily. • Count clock is selectable among 6 internal clocks. ...
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... Re- versed PPG output control circuit Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01) MB90385 Series “H” level side data bus “L” level side data bus Re- served Interrupt R request output ...
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... CLK PPG output control circuit MD0 (512/HCLK) 3 Count clock Select signal selector PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01) “H” level side data bus “L” level side data bus Re- served Interrupt request output Pin ...
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... Delay interrupt request generation/release register (DIRR) Generates or releases delay interrupt request. Interrupt number An interrupt number used in delay interrupt generation module is as follows: Interrupt number: #42 ( MB90385 Series Function and control Internal data bus R0 S Interrupt request R Latch Interrupt request signal 45 ...
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... I/O service (EI If the expanded intelligent I/O service (EI external interrupt function is enabled and branches to interrupt processing. If the has been enabled, (ICR: ISE=1), DTP function is enabled and automatic data transmission is performed OS. After performing specified number of data transmission processes, the process branches to interrupt processing. ...
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... DTP/External interrupt/CAN wakeup block diagram Detection level setting register (ELVR) LB7 LA7 LB6 LA6 Pin INT7 Pin INT6 Pin INT5 Pin INT4 DTP/external interrupt input detection circuit Interrupt request signal Re- Re- Re- Re- LB5 LA5 LB4 LA4 served served served served Level/edge ...
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... OS is allowed upon occurrence of an interrupt request. With use of EI even if A/D conversion is performed successively. • An activation trigger is selectable among software trigger, internal timer output, and external trigger (fall edge). *: When operating with 16-MHz machine clock 8/10-bit A/D converter conversion mode ...
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... Analog AN4 channel AN3 selector AN2 AN1 AN0 A/D data register S10 ST1 ST0 CT1 CT0 (ADCR Internal timer output : Not defined Reserved : Be sure to set to “0” : Machine clock Interrupt request output Re- MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 served ...
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... Asynchronous mode 0 (normal mode) 1 Multi processor mode 2 Synchronous mode : Disallowed *1 : “+1” address/data selection bit used for communication control (bit 11 of SCR1 register: A/D Only 1 bit is detected as a stop bit on data reception OS. Description Full-duplex double buffer Clock synchronous (No start/stop bit, no parity bit) Clock asynchronous (start-stop synchronous) Built-in special-purpose baud-rate generator ...
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... DIV1 DIV0 Control bus Transmission clock Reception Transmission control control circuit circuit Transmission Start bit start circuit detection circuit Reception bit Transmission counter bit counter Transmission Reception parity counter parity counter Shift register for Shift register for transmission reception Recep- tion ...
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MB90385 Series 12. CAN Controller The Controller Area Network (CAN serial communication protocol compliant with CANVer2.0A and Ver2.0B. The protocol allows data transmission and reception in both standard frame format and expanded frame format. Features of CAN controller ...
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... Bit error Reception buffer Acknowledgment decision circuit ACK error error check Reception buffer Form error Reception buffer, transmission buffer, reception DLC, transmission DLC, ID selection MB90385 Series Idle, interrupt, suspend, Bus transmit, receive, error, and overload Error frame generation circuit Overload frame ...
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... MB90385 Series 13. Address Matching Detection Function Outline The address matching detection function checks if an address of an instruction to be processed next to a currently- processed instruction is identical with an address specified in the detection address register. If the addresses match with each other, an instruction to be processed next in program is forcibly replaced with INT9 instruction, and process branches to the interrupt process program ...
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... ROM Mirror Function Selection Module Outline The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. ROM mirror function selection module block diagram Reserved Reserved Reserved Address FF bank Data FF bank access by ROM mirror function ...
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... Writing/deleting on flash memory is performed by instruction from CPU via flash memory interface. Because rewriting is allowed on mounted memory, modifying program and data is performed efficiently. Features of 512 Kbit flash memory • 128 K words x 8 bits/64 K words x 16 bits ( sector configuration • Automatic program algorithm (Embedded Algorithm • Built-in deletion pause/deletion resume function • ...
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... Sector configuration For access from CPU, SA0 to SA3 are allocated in FF bank register. Sector configuration of 512 Kbit flash memory Flash memory SA0 (32 Kbytes) SA1 (8 Kbytes) SA2 (8 Kbytes) SA3 (16 Kbytes “Writer address” address equivalent to CPU address, which is used when data is written on flash memory, using parallel writer. When writing/ deleting data with general-purpose writer, the writer address is used for writing and deleting ...
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... MB90385 Series ELECTRIC CHARACTERISTICS 1. Absolute Maximum Rating Parameter Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “ ...
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... Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass through the protective diode and increase the potential at the V devices. ...
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... Operating temperature Use a ceramic capacitor capacitor of similar frequency characteristics. On the Vcc pin, use a bypass capacitor that has a larger capacity than that of Cs. Refer to the following figure for connection of smoothing capacitor Cs AVcc is a voltage at which accuracy is guaranteed. AVcc should not exceed Vcc. ...
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... DC Characteristics Parame- Sym Pin name ter bol CMOS “H” level V hysteresis input IHS input pin voltage V MD input pin IHM CMOS “L” level V hysteresis input ILS input pin voltage V MD input pin ILM Pins other than V V “H” level ...
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... Internally operating at 8 kHz, subclock oper- ation, — 5 Internally operating at 8 kHz, subclock, — 10 sleep mode 5 Internally operating at — 8 kHz, clock mode Stopping, — — 0 105 Unit Remarks Max 1.2 mA MB90F387/S 100 A MB90387 100 k FLASH product is 100 k not provided with pull-down resistor. ...
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... Internal operation clock cycle time t LCP *1 : Internal operation clock frequency should not exceed 16 MHz When selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned in “Relation among external clock frequency and internal clock frequency”. Clock timing X0 X0A (V 5 ...
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MB90385 Series PLL operation guarantee range 5.5 4.0 3.5 3.0 1.5 Relation among external clock frequency and internal clock frequency MHz at maximum when crystal or ceramic resonator circuit is ...
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... Value Min Max Oscillation time of oscillator 100 100 (internal operation clock cycle time RSTL 0 100 time of Wait time for stabilizing oscillation MB90385 Series Unit Remarks ns Normal operation In sub clock sub 2 2 sleep* , watch* and stop mode s In timebase timer Execute instruction 65 ...
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... V CC 0.2 V Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown below. When raising the power, do not use PLL clock. Howev- er, if voltage drop is 1V/s or less, use of PLL clock is allowed during operation. ...
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UART timing Parameter Symbol Pin name Serial clock cycle time t SCYC SCK SOT delay time t SLOV Valid SIN SCK t SCK valid SIN hold time t Serial clock “H” pulse width t Serial clock “L” pulse width ...
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MB90385 Series Internal shift clock mode SCK SOT SIN External shift clock mode SCK SOT SIN 68 t SCYC 2 SLOV 2 IVSH SHIX 0 0 ...
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Timer input timing Parameter Symbol t TIWH Input pulse width t TIWL * : Refer to "(1) Clock timing" ratings for t Timer input timing 0.8 V TIN0, TIN1, IN0 to IN3 (6) Trigger input timing Parameter Symbol t ...
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MB90385 Series 5. A/D converter ( Parameter Symbol Resolution Total error Nonlinear error Differential linear error Zero transition voltage V OT Full-scale transition V FST voltage Compare time Sampling time Analog port input I AIN current Analog ...
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... Differential linear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an error ideal value. Total error : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. 3FF 3FE 3FD ...
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... Actual conversion characteristics 3FE {1 LSB ( 3FD 004 003 002 Ideal characteristics 001 V (actual measurement value) OT AVss Analog input Linear error of digital output N Differential linear error of digital output Voltage at which digital output transits from “000 Voltage at which digital output transits from “3FE FST ...
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... Recommended output impedance of external circuits are: Approx. 3.9 k (sampling period=2. 16-MHz machine clock), Approx lower (4.0 V period=8 16-MHz machine clock external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. ...
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... MB90385 Series EXAMPLE CHARACTERISTICS MB90F387 2 2.5 350 300 250 200 150 100 external clock operation MHz MHz MHz MHz MHz 3.5 4.5 5.5 6 CCS external clock operation MHz MHz MHz MHz MHz 3.5 4.5 5 CCL external clock operation kHz ...
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... I V CCLS ( CCT ( CCH (V) CC MB90385 Series external clock operation A f Internal operating frequency kHz external clock operation A f Internal operating frequency kHz 6 7 Stopping (Continued) 75 ...
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MB90385 Series (Continued) 1000 900 800 700 600 500 400 300 200 100 0 0 1000 900 800 700 600 500 400 300 200 100 2 ...
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MB90387 2 2.5 100 ...
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... MB90385 Series CCLS external clock operation kHz ( CCT external clock operation kHz ( CCH CC Stopping (V) CC Internal operating frequency 7 Internal operating frequency (Continued) ...
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H level input voltage/ L level input voltage ...
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MB90385 Series ORDERING INFORMATION Part number MB90F387PMT MB90387PMT MB90F387SPMT MB90387SPMT 80 Package 48-pin plastic LQFP (FPT-48P-M26) Remarks ...
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PACKAGE DIMENTION 48-pin plastic LQFP (FPT-48P-M26) 9.00±0.20(.354±.008)SQ +0.40 +.016 * 7.00 .276 SQ –0.10 –.004 INDEX 48 LEAD No 0.50(.020) 0.20±0.05 (.008±.002) 2003 FUJITSU LIMITED F48040S-c-2-2 C MB90385 Series Note These dimensions ...
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... and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic ...