MPC8349E-MITXE Freescale Semiconductor, MPC8349E-MITXE Datasheet - Page 35
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MPC8349E-MITXE
Manufacturer Part Number
MPC8349E-MITXE
Description
BOARD REFERENCE FOR MPC8349
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II™ PROr
Type
MPUr
Specifications of MPC8349E-MITXE
Contents
Module and Misc Hardware
Processor To Be Evaluated
MPC8349E
Interface Type
Ethernet, USB
Silicon Manufacturer
Freescale
Core Architecture
Power Architecture
Core Sub-architecture
PowerQUICC
Silicon Core Number
MPC83xx
Silicon Family Name
PowerQUICC II PRO
Rohs Compliant
Yes
For Use With/related Products
MPC8349E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MPC8349E-MITXE
1.6.4.1
CLKIN is the input to the CCB PLL to generate the CCB clock, which provides the platform logic.
Table 22
ratios.
Freescale Semiconductor
12–15
16–17
18–19
20–27
9–11
Bits
28
29
30
31
8
shows the common combinations of CLKIN, CCB, and the core frequency and their respective
Reset Configuration Word SPMF[0–3] and COREPLL[0–6]
Table 21. Reset Configuration Word High (RCWH) Bit Descriptions (continued)
ROMLOC
Reserved
Reserved
Reserved
TSEC1M
TSEC2M
SWEN
Name
LALE
LDP
TLE
MPC8349E-mITXE Reference Design Platform User’s Guide, Rev. 2
Software watchdog
enable
Boot ROM
interface location
—
TSEC1 Mode
TSEC2 Mode
—
True little endian
Local Bus ALE
signal timing
LDP/CKSTP pin
mux state after
reset
—
Preliminary—Subject to Change Without Notice
Meaning
0: Default
1
000
001
010
011, 100
101
110: Default
111
Must be cleared
00
01
10: Default
10
00
01
10: Default
10
Must be cleared
0: Default
1
0: Default
1
0: Default
1
Must be cleared
Disabled
Enabled
DDR SDRAM
PCI1
PCI2
Reserved
Local bus GPCM, 8 bits
Local bus GPCM, 16 bits
Local bus GPCM, 32 bits
RGMII
RTBI
GMII
TBI
RGMII
RTBI
GMII
TBI
Big-endian mode
True little endian mode
Normal LALE timing
LALE is negated 1/2 lbiu_controller_clk earlier.
LDP[0] and
LDP[1] = local data parity.
LDP[0] = CKSTOP_OUT and LDP[1] =
CKSTOP_IN.
Detailed Description
MPC8349E-mITXE Board
35