101-0681 Rabbit Semiconductor, 101-0681 Datasheet - Page 86
101-0681
Manufacturer Part Number
101-0681
Description
KIT DEVELOPMENT RCM3700 INT'L
Manufacturer
Rabbit Semiconductor
Series
RabbitCore 3000r
Type
MPU Moduler
Datasheet
1.101-0522.pdf
(169 pages)
Specifications of 101-0681
Contents
RabbitCore Module, Dev. Board, AC Adapter, Cable and Dynamic C® CD-Rom
Processor To Be Evaluated
Rabbit 3000
Interface Type
Ethernet
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
4.75 V to 5.25 V
For Use With/related Products
RCM3700
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
101-681
101-681
101-681
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
101-0681
Manufacturer:
Rabbit
Quantity:
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Table A-4 lists the delays in gross memory access time.
The measurements are taken at the 50% points under the following conditions.
• T = -40°C to 85°C, V = V
• Internal clock to nonloaded CLK pin delay 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
• T
• T
• T
• T
• T
• T
The data setup time delays are similar for both T
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.
Technical Note TN227, Interfacing External I/O with Rabbit 2000/3000 Designs, con-
tains suggestions for interfacing I/O devices to the Rabbit 3000 microprocessors.
RabbitCore RCM3700 User’s Manual
Table A-4. Data and Clock Delays VIN ±10%, Temp, -40°C–+85°C (maximum)
adr
CSx
IOCSx
IORD
IOWR
BUFEN
3.3 V
VIN
, the clock to address delay
, the clock to memory chip select delay
, the clock to I/O read strobe delay
, the clock to I/O write strobe delay
, the clock to I/O chip select delay
, the clock to I/O buffer enable delay
Clock to Address Output Delay
30 pF
6
60 pF
(ns)
DD
8
±10%
90 pF
11
Data Setup
Time Delay
setup
(ns)
and T
1
hold
Spectrum Spreader Delay
.
no dbl/dbl
Normal
3/4.5
(ns)
no dbl/dbl
Strong
4.5/9
84
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