DEMO9S08EL32AUTO Freescale Semiconductor, DEMO9S08EL32AUTO Datasheet - Page 56

• Manufacturer Part Number: DEMO9S08EL32AUTO
• Description: DEMO BOARD EL32 AUTO
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08EL32AUTO

• Contents: Board, Cable, CD and Documentation
• Processor To Be Evaluated: MC9S08EL32
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 12 V
• For Use With/related Products: MC9S08EL32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Memory
Table 4-7
56
PRDIV8
DIVLD
Field
DIV
5:0
7
6
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH and EEPROM.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH and EEPROM.
Prescale (Divide) FLASH and EEPROM Clock by 8
0 Clock input to the FLASH and EEPROM clock divider is the bus rate clock.
1 Clock input to the FLASH and EEPROM clock divider is the bus rate clock divided by 8.
Divisor for FLASH and EEPROM Clock Divider — The FLASH and EEPROM clock divider divides the bus rate
clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting
frequency of the internal FLASH and EEPROM clock must fall within the range of 200 kHz to 150 kHz for proper
FLASH operations. Program/Erase timing pulses are one cycle of this internal FLASH and EEPROM clock which
corresponds to a range of 5 μs to 6.7 μs. The automated programming logic uses an integer number of these
pulses to complete an erase or program operation. See
200 kHz
150 kHz
20 MHz
10 MHz
8 MHz
4 MHz
2 MHz
1 MHz
f
Bus
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
(Binary)
PRDIV8
Table 4-7. FLASH and EEPROM clock divider Settings
if PRDIV8 = 1 — f
1
0
0
0
0
0
0
0
if PRDIV8 = 0 — f
Table 4-6. FCDIV Register Field Descriptions
(Decimal)
DIV
12
49
39
19
9
4
0
0
FCLK
FCLK
= f
192.3 kHz
= f
Bus
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
f
FCLK
Description
Bus
÷ (8 × (DIV + 1))
÷ (DIV + 1)
Equation 4-1
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
and
Equation
5.2 μs
6.7 μs
5 μs
5 μs
5 μs
5 μs
5 μs
5 μs
4-2.
Freescale Semiconductor
Eqn. 4-1
Eqn. 4-2