M52259EVB Freescale Semiconductor, M52259EVB Datasheet - Page 6
M52259EVB
Manufacturer Part Number
M52259EVB
Description
BOARD EVAL FOR 52259 COLDFIRE V2
Manufacturer
Freescale Semiconductor
Series
ColdFire®r
Type
MCUr
Datasheet
1.M52259EVB.pdf
(46 pages)
Specifications of M52259EVB
Contents
Board, Cables, Documentation, DVD, Flash Drive and Power Supply
Processor To Be Evaluated
MCF52259
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB
Silicon Manufacturer
Freescale
Core Architecture
Coldfire
Core Sub-architecture
Coldfire V2
Silicon Core Number
MCF52
Silicon Family Name
MCF5225x
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MCF52259
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale Semiconductor
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— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic
Fast Ethernet controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
Mini-FlexBus
— External bus interface available on 144 pin packages
— Supports glueless interface with 8-bit ROM/flash/SRAM/simple slave peripherals. Can address up to 2 Mbytes of
— 2 chip selects (FB_CS[1:0])
— Non-multiplexed mode: 8-bit dedicated data bus, 20-bit address bus
— Multiplexed mode: 16-bit data and 20-bit address bus
— FB_CLK output to support synchronous memories
— Programmable base address, size, and wait states to support slow peripherals
— Operates at up to 40 MHz (bus clock) in 1:2 mode or up to 80 MHz (core clock) in 1:1 mode
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
Two I
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to three chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 s conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
addresses
2
C modules
MCF52259 ColdFire Microcontroller, Rev. 4
2
C bus
Family Configurations
6