EDK2638 Renesas Electronics America, EDK2638 Datasheet - Page 4

• Manufacturer Part Number: EDK2638
• Description: DEV EVALUATION KIT H8S/2638
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of EDK2638

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8S/2638
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

HWR
LWR
RD
1-C4
1-C4
1-C4
PF4
PF3
PF5
GROUND
GROUND
UVCC
2
1
SN74HC08PWR
1
2
4
5
9
10
12
13
VCC=UVCC
A0 is connected to A0 of the SRAM, for 8-bit mode purposes.
This halves the available address space of the SRAM.
U2
&
11
3
6
8
1-D3
1-C4
PA1
CSn
Option to disable A17 when using SCI2
However memory size is reduced
as A17 will not be available.
WEn
UBn
LBnLOGIC
Option to disable LB for
8-bit mode on the user jumper block.
This frees up the port normally used for
the lower data bus.
3-D2
3-D2
LBn
R5
1
0R
2
GROUND
1-C4
1-C4
1-C4
1-C4
1-C4
1-C4
1-C4
1-C4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-B4
1-D3
1-D3
1-D3
1-D3
1-D3
1-D3
1-D3
1-D3
1-C3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Port E is the Lower Data Bus
Port D is the Upper Data Bus
HM6216255HCLTT-10
18
19
20
21
22
23
24
25
26
27
42
43
44
41
17
40
39
10
13
14
15
16
29
30
31
32
35
36
37
38
1
2
3
4
5
6
7
8
9
VCC=UVCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CSn
OEn
WEn
UBn
LBn
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
4MBit
U1
HITACHI MICRO SYSTEMS EUROPE LTD
DRAWN BY
SCHEMATIC TITLE
SHEET TITLE
A.G.M.
Whitebrook Park, Maidenhead, Berkshire
GROUND
External SRAM and Glue Logic
UVCC
2
1
For Evaluation Purposes
11-01-02
2
1
DATE
UNITED KINGDOM
EDK 2638
REV DRAWING NUMBER PAGE
1
D003500_04
SIZE A4
4
5