EDK2676 Renesas Electronics America, EDK2676 Datasheet - Page 8

• Manufacturer Part Number: EDK2676
• Description: DEV EVALUATION KIT H8S/2676T
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of EDK2676

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/2676T
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.4. M
Table 4-4 illustrates the EDK memory map for mode 4.
4.5. SRAM A
External access timing is defined by several registers, allowing different types of devices to be addressed. Recommended
register settings for the selection of wait states and signal extensions specific to this EDK are given below
Please refer to the hardware manual for the microcontroller for more information on these register settings.
4.6. LED
The EDK has four red LEDs. The function of each LED is clearly marked on the silk screen of the PCB. Please refer to the
board layout diagram for position information (Section 3).
When the board is connected to a power source the Power (PWR) led will illuminate. The Boot mode indication LED will
illuminate when the microcontroller has been placed into Boot mode. Please see section 5 for more details of this function.
There are two LEDs dedicated for user control, these are marked USR1 and USR2. Each LED will illuminate when the port
pin is in a logical high state.
BCR
DRAMCR
ABWCR
RDNCR
ASTCR
WTCRBL
CSACRH
CSACRL
PFCR0
PFCR2
PADDR
PBDDR
PCDDR
PGDDR
Register
EMORY
S
H'FECC
H'FED0
H'FEC0
H'FEC6
H'FEC1
H'FEC5
H'FEC8
H'FEC9
H'FE32
H'FE34
H'FE29
H'FE2A
H'FE2B
H'FE2F
Address
M
CCESS
AP
H’00000000
H’0003FFFF
H’00040000
H’001FFFFF
H’00200000
H’0027FFFF
H’00280000
H’00FF9FFF
H’00FFA000
H’00FFBFFF
H’00FFC000
H’00FFFBFF
H’00FFFC00
H’00FFFEFF
H’00FFFF00
H’00FFFF1F
H’00FFFF20
H’00FFFFFF
T
IMING
0x1C04
0x00 (Default)
0x00
0x00 (Default)
0xFF (Default)
0x10
0x00 (Default)
0x00 (Default)
0x02
0x04
0xFF
0xFF
0xFE
0x02
Setting for EDK
Recommended
Section Start
Section End
T
ABLE
T
ABLE
4-5: SRAM A
16-bit register used for Idle Cycle Settings
Configures DRAM Interface Settings. This value allows OEn/(CKE) to be used
as I/O pin
Selects 2 or 3 state access space (3 is selected for this value)
Selects read strobe (RDn) negation timing
Selects 2 or 3 state space
Selects number of program wait states for each area
Selects extension of Chip select signals for each access space
Selects extension of Chip select signals for each access space
Port Function Control Register 0 (Selects functions of specific port pins)
Port Function Control Register 2 (Selects functions of specific port pins)
Specifies directionality of port A pins
Specifies directionality of port B pins
Specifies directionality of port C pins
Specifies directionality of port G pins
4-4: M
EMORY
CCESS
On-Chip ROM
External Address Space
External RAM
External Address Space
On-Chip RAM / External Address Space
External Address Space
Internal I/O Registers
External Address Space
Internal I/O Registers
M
AP
C
(D
ONTROL
EFAULT
Section Allocation
R
M
EGISTERS
ODE
4)
Function
8