MPC8378E-MDS-PB Freescale Semiconductor, MPC8378E-MDS-PB Datasheet - Page 88

• Manufacturer Part Number: MPC8378E-MDS-PB
• Description: BOARD PROCESSOR FOR MDS S
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8378E-MDS-PB

• Contents: Board
• For Use With/related Products: MPC8378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Speed Serial Interfaces (HSSI)
Figure 62
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
20.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 67
88
At recommended operating conditions with XV
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Clock Driver
Single-Ended CLK
Driver Chip
describes some AC parameters common to SGMII and PCI Express protocols.
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Parameter
Table 67. SerDes Reference Clock Common AC Parameters
Figure 62. Single-Ended Connection (Reference Only)
33 Ω
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
DD_SRDS
100 Ω differential PWB trace
or XV
DD_SRDS
= 1.0 V ± 5%.
Rise Edge Rate
Fall Edge Rate
Symbol
V
V
IH
IL
SDn_REF_CLK
SDn_REF_CLK
Min
200
1.0
1.0
—
50 Ω
50 Ω
–200
Max
4.0
4.0
—
Freescale Semiconductor
MPC8378E
SerDes Refer.
CLK Receiver
Unit
V/ns
V/ns
mV
mV
Notes
2, 3
2, 3
2
2